Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	741986570	5583626	0	0
wdog_bark_thold_rd_A	741986570	150120	0	0
wdog_bite_thold_rd_A	741986570	133688	0	0
wdog_ctrl_rd_A	741986570	130569	0	0
wdog_regwen_rd_A	741986570	152135	0	0
wkup_ctrl_rd_A	741986570	132650	0	0
wkup_thold_hi_rd_A	741986570	151372	0	0
wkup_thold_lo_rd_A	741986570	131489	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741986570	5583626	0	0
T7	290107	80395	0	0
T8	10609	0	0	0
T9	117220	36913	0	0
T10	167924	0	0	0
T11	959544	359305	0	0
T12	262473	0	0	0
T13	913724	0	0	0
T29	20558	0	0	0
T30	0	158696	0	0
T31	0	140021	0	0
T36	0	138995	0	0
T37	0	85451	0	0
T38	0	73822	0	0
T39	0	101441	0	0
T40	0	59384	0	0
T41	50546	0	0	0
T42	281005	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741986570	150120	0	0
T25	0	7396	0	0
T81	794102	17457	0	0
T82	483172	10638	0	0
T83	0	15479	0	0
T84	0	1203	0	0
T86	0	4407	0	0
T87	283497	4107	0	0
T88	0	12889	0	0
T89	0	9899	0	0
T90	0	6634	0	0
T91	12434	0	0	0
T92	162262	0	0	0
T93	20151	0	0	0
T94	42132	0	0	0
T95	458722	0	0	0
T96	307280	0	0	0
T97	12065	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741986570	133688	0	0
T25	0	7159	0	0
T81	794102	16052	0	0
T82	483172	9256	0	0
T83	0	14118	0	0
T84	0	919	0	0
T86	0	3547	0	0
T87	283497	3298	0	0
T88	0	11928	0	0
T89	0	9156	0	0
T90	0	5706	0	0
T91	12434	0	0	0
T92	162262	0	0	0
T93	20151	0	0	0
T94	42132	0	0	0
T95	458722	0	0	0
T96	307280	0	0	0
T97	12065	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741986570	130569	0	0
T25	0	6574	0	0
T81	794102	15612	0	0
T82	483172	8975	0	0
T83	0	13474	0	0
T84	0	996	0	0
T86	0	3675	0	0
T87	283497	3370	0	0
T88	0	11146	0	0
T89	0	9052	0	0
T90	0	5411	0	0
T91	12434	0	0	0
T92	162262	0	0	0
T93	20151	0	0	0
T94	42132	0	0	0
T95	458722	0	0	0
T96	307280	0	0	0
T97	12065	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741986570	152135	0	0
T25	0	7452	0	0
T81	794102	18440	0	0
T82	483172	10098	0	0
T83	0	15808	0	0
T84	0	1073	0	0
T86	0	4269	0	0
T87	283497	3742	0	0
T88	0	13064	0	0
T89	0	10130	0	0
T90	0	6403	0	0
T91	12434	0	0	0
T92	162262	0	0	0
T93	20151	0	0	0
T94	42132	0	0	0
T95	458722	0	0	0
T96	307280	0	0	0
T97	12065	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741986570	132650	0	0
T25	0	6466	0	0
T81	794102	15657	0	0
T82	483172	9447	0	0
T83	0	13851	0	0
T84	0	956	0	0
T86	0	3746	0	0
T87	283497	3558	0	0
T88	0	11575	0	0
T89	0	8798	0	0
T90	0	5747	0	0
T91	12434	0	0	0
T92	162262	0	0	0
T93	20151	0	0	0
T94	42132	0	0	0
T95	458722	0	0	0
T96	307280	0	0	0
T97	12065	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741986570	151372	0	0
T25	0	7549	0	0
T81	794102	17884	0	0
T82	483172	10411	0	0
T83	0	15852	0	0
T84	0	1139	0	0
T86	0	4157	0	0
T87	283497	3668	0	0
T88	0	12675	0	0
T89	0	10541	0	0
T90	0	6232	0	0
T91	12434	0	0	0
T92	162262	0	0	0
T93	20151	0	0	0
T94	42132	0	0	0
T95	458722	0	0	0
T96	307280	0	0	0
T97	12065	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	741986570	131489	0	0
T25	0	6598	0	0
T81	794102	15365	0	0
T82	483172	9210	0	0
T83	0	14665	0	0
T84	0	883	0	0
T86	0	3381	0	0
T87	283497	3171	0	0
T88	0	11524	0	0
T89	0	8637	0	0
T90	0	5620	0	0
T91	12434	0	0	0
T92	162262	0	0	0
T93	20151	0	0	0
T94	42132	0	0	0
T95	458722	0	0	0
T96	307280	0	0	0
T97	12065	0	0	0