Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	300939	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	3670422	1		T1	14		T2	245		T3	29885

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	976531	1		T1	1		T2	43		T3	7917
values[0x0]	1404676	1		T1	8		T2	167		T3	11485
values[0x1]	1590154	1		T1	11		T2	145		T3	13132

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	135301	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	3836060	1		T1	14		T2	267		T3	31325

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14716	1		T3	140		T10	474		T13	1
valid_sources[0x01]	16435	1		T2	2		T3	122		T6	1
valid_sources[0x02]	17564	1		T3	145		T10	508		T13	5
valid_sources[0x03]	16304	1		T3	133		T10	688		T14	350
valid_sources[0x04]	14225	1		T2	1		T3	120		T10	520
valid_sources[0x05]	16090	1		T2	5		T3	146		T10	693
valid_sources[0x06]	16050	1		T2	2		T3	139		T4	3
valid_sources[0x07]	14943	1		T3	139		T10	480		T13	1
valid_sources[0x08]	16981	1		T3	125		T4	3		T9	1
valid_sources[0x09]	15086	1		T2	3		T3	129		T4	2
valid_sources[0x0a]	15575	1		T2	1		T3	131		T4	2
valid_sources[0x0b]	15712	1		T2	12		T3	120		T10	66
valid_sources[0x0c]	15094	1		T3	125		T10	482		T14	340
valid_sources[0x0d]	16203	1		T2	2		T3	126		T10	1178
valid_sources[0x0e]	15234	1		T2	3		T3	149		T10	303
valid_sources[0x0f]	15458	1		T2	1		T3	104		T10	784
valid_sources[0x10]	16561	1		T3	127		T4	3		T10	357
valid_sources[0x11]	14919	1		T3	126		T7	3		T10	466
valid_sources[0x12]	15929	1		T3	121		T10	426		T13	3
valid_sources[0x13]	13700	1		T3	138		T4	1		T10	265
valid_sources[0x14]	15481	1		T3	126		T4	2		T6	1
valid_sources[0x15]	14613	1		T2	6		T3	117		T10	71
valid_sources[0x16]	14940	1		T3	122		T6	1		T10	670
valid_sources[0x17]	16278	1		T2	6		T3	138		T10	725
valid_sources[0x18]	15739	1		T3	122		T4	2		T10	147
valid_sources[0x19]	13395	1		T2	2		T3	108		T4	8
valid_sources[0x1a]	14785	1		T2	1		T3	130		T10	504
valid_sources[0x1b]	15626	1		T2	2		T3	122		T4	17
valid_sources[0x1c]	15671	1		T2	1		T3	120		T4	6
valid_sources[0x1d]	14484	1		T2	1		T3	132		T4	7
valid_sources[0x1e]	14171	1		T3	139		T10	817		T13	2
valid_sources[0x1f]	15191	1		T2	5		T3	129		T10	778
valid_sources[0x20]	16251	1		T2	1		T3	118		T10	552
valid_sources[0x21]	15729	1		T3	119		T10	684		T14	339
valid_sources[0x22]	14054	1		T3	136		T10	236		T14	375
valid_sources[0x23]	15164	1		T3	121		T4	2		T10	388
valid_sources[0x24]	15027	1		T2	3		T3	120		T10	449
valid_sources[0x25]	15604	1		T2	1		T3	145		T10	1052
valid_sources[0x26]	14751	1		T2	1		T3	100		T10	822
valid_sources[0x27]	16316	1		T2	1		T3	119		T10	702
valid_sources[0x28]	15016	1		T2	2		T3	117		T4	9
valid_sources[0x29]	15900	1		T3	133		T6	1		T10	175
valid_sources[0x2a]	14815	1		T3	112		T10	840		T13	1
valid_sources[0x2b]	17648	1		T2	1		T3	124		T4	1
valid_sources[0x2c]	15390	1		T3	127		T10	1165		T13	2
valid_sources[0x2d]	15463	1		T2	7		T3	126		T4	1
valid_sources[0x2e]	16184	1		T3	123		T4	6		T10	681
valid_sources[0x2f]	17116	1		T3	137		T10	875		T14	351
valid_sources[0x30]	14797	1		T3	119		T10	654		T13	1
valid_sources[0x31]	14907	1		T2	1		T3	123		T10	102
valid_sources[0x32]	14420	1		T3	124		T4	4		T10	1085
valid_sources[0x33]	14756	1		T3	137		T10	512		T13	4
valid_sources[0x34]	14773	1		T3	126		T10	360		T14	359
valid_sources[0x35]	14899	1		T3	126		T10	1064		T14	349
valid_sources[0x36]	15566	1		T3	118		T10	409		T13	3
valid_sources[0x37]	15274	1		T3	130		T4	7		T10	578
valid_sources[0x38]	16269	1		T2	1		T3	114		T6	1
valid_sources[0x39]	15556	1		T2	3		T3	115		T10	902
valid_sources[0x3a]	15865	1		T3	126		T10	386		T14	346
valid_sources[0x3b]	14882	1		T3	122		T4	1		T10	712
valid_sources[0x3c]	15261	1		T3	134		T4	27		T10	676
valid_sources[0x3d]	15064	1		T2	7		T3	158		T10	723
valid_sources[0x3e]	15188	1		T1	8		T2	2		T3	138
valid_sources[0x3f]	13780	1		T2	1		T3	121		T10	632
valid_sources[0x40]	15498	1		T3	132		T10	469		T14	358
valid_sources[0x41]	14838	1		T3	116		T10	239		T14	336
valid_sources[0x42]	16748	1		T3	154		T4	2		T10	680
valid_sources[0x43]	16017	1		T2	1		T3	117		T4	6
valid_sources[0x44]	15387	1		T2	16		T3	158		T10	763
valid_sources[0x45]	14515	1		T3	122		T4	5		T7	1
valid_sources[0x46]	14528	1		T3	117		T10	565		T13	6
valid_sources[0x47]	15576	1		T3	108		T10	990		T14	399
valid_sources[0x48]	15943	1		T2	3		T3	129		T4	6
valid_sources[0x49]	16333	1		T3	117		T10	1430		T12	1
valid_sources[0x4a]	15931	1		T2	4		T3	124		T10	753
valid_sources[0x4b]	15404	1		T2	1		T3	126		T4	2
valid_sources[0x4c]	14434	1		T2	1		T3	121		T10	530
valid_sources[0x4d]	15546	1		T3	128		T4	4		T10	505
valid_sources[0x4e]	17148	1		T3	104		T10	852		T13	1
valid_sources[0x4f]	16800	1		T3	133		T4	2		T10	1069
valid_sources[0x50]	13418	1		T2	2		T3	120		T4	7
valid_sources[0x51]	15112	1		T2	3		T3	123		T4	3
valid_sources[0x52]	15323	1		T3	146		T10	943		T14	367
valid_sources[0x53]	15412	1		T2	1		T3	141		T10	1125
valid_sources[0x54]	14122	1		T3	116		T10	288		T14	375
valid_sources[0x55]	15817	1		T3	145		T4	1		T10	416
valid_sources[0x56]	15425	1		T3	121		T4	1		T6	3
valid_sources[0x57]	14150	1		T2	1		T3	125		T10	452
valid_sources[0x58]	16171	1		T3	154		T10	533		T14	341
valid_sources[0x59]	15036	1		T3	119		T10	644		T14	371
valid_sources[0x5a]	15114	1		T2	10		T3	134		T10	532
valid_sources[0x5b]	15536	1		T3	125		T10	634		T13	5
valid_sources[0x5c]	16525	1		T2	1		T3	147		T10	1105
valid_sources[0x5d]	16023	1		T3	125		T10	1216		T14	342
valid_sources[0x5e]	16437	1		T2	3		T3	131		T10	499
valid_sources[0x5f]	14358	1		T3	119		T10	680		T14	309
valid_sources[0x60]	16562	1		T3	133		T4	5		T10	1138
valid_sources[0x61]	15700	1		T2	1		T3	119		T10	905
valid_sources[0x62]	17001	1		T3	143		T10	915		T14	350
valid_sources[0x63]	15251	1		T2	1		T3	113		T10	1011
valid_sources[0x64]	16978	1		T3	139		T10	487		T13	2
valid_sources[0x65]	16007	1		T3	139		T10	725		T14	358
valid_sources[0x66]	14266	1		T2	3		T3	114		T4	5
valid_sources[0x67]	17184	1		T3	117		T10	1256		T14	324
valid_sources[0x68]	14168	1		T3	113		T10	695		T13	2
valid_sources[0x69]	15622	1		T3	143		T10	384		T14	361
valid_sources[0x6a]	14854	1		T2	8		T3	134		T4	7
valid_sources[0x6b]	15619	1		T3	145		T4	9		T10	647
valid_sources[0x6c]	15176	1		T3	116		T10	402		T13	8
valid_sources[0x6d]	16327	1		T3	114		T10	590		T13	2
valid_sources[0x6e]	14445	1		T2	4		T3	141		T10	886
valid_sources[0x6f]	15013	1		T3	128		T4	2		T10	885
valid_sources[0x70]	14439	1		T2	1		T3	131		T4	2
valid_sources[0x71]	15633	1		T3	100		T10	1161		T13	2
valid_sources[0x72]	17001	1		T3	132		T10	716		T13	1
valid_sources[0x73]	15894	1		T2	1		T3	122		T9	4
valid_sources[0x74]	15599	1		T3	142		T10	691		T14	394
valid_sources[0x75]	14789	1		T3	120		T4	6		T10	289
valid_sources[0x76]	17906	1		T3	124		T10	1105		T13	3
valid_sources[0x77]	15384	1		T2	1		T3	98		T10	727
valid_sources[0x78]	16755	1		T3	139		T4	6		T6	1
valid_sources[0x79]	16449	1		T3	112		T10	815		T14	369
valid_sources[0x7a]	16363	1		T2	2		T3	116		T4	4
valid_sources[0x7b]	16306	1		T3	142		T10	931		T13	1
valid_sources[0x7c]	15245	1		T2	6		T3	143		T10	444
valid_sources[0x7d]	16446	1		T3	151		T7	5		T10	1475
valid_sources[0x7e]	15981	1		T3	120		T10	487		T13	3
valid_sources[0x7f]	16252	1		T3	129		T10	401		T13	4
valid_sources[0x80]	13857	1		T3	146		T8	22		T10	780

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

914539

1

T2

23

T3

7392

T4

15

values[0x0]

all_enables

biggest_size

1378924

1

T1

6

T2

121

T3

11248

values[0x1]

all_enables

biggest_size

1376959

1

T1

8

T2

101

T3

11245