Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	714842073	4343846	0	0
wdog_bark_thold_rd_A	714842073	90935	0	0
wdog_bite_thold_rd_A	714842073	79287	0	0
wdog_ctrl_rd_A	714842073	79518	0	0
wdog_regwen_rd_A	714842073	91325	0	0
wkup_ctrl_rd_A	714842073	80202	0	0
wkup_thold_hi_rd_A	714842073	89579	0	0
wkup_thold_lo_rd_A	714842073	78551	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714842073	4343846	0	0
T3	148876	38063	0	0
T4	117983	0	0	0
T5	8600	0	0	0
T6	55103	0	0	0
T7	10120	0	0	0
T8	38218	0	0	0
T9	14285	0	0	0
T10	467285	167537	0	0
T11	841128	0	0	0
T12	25139	0	0	0
T14	0	100477	0	0
T15	0	203080	0	0
T30	0	24867	0	0
T31	0	11546	0	0
T32	0	264731	0	0
T33	0	198071	0	0
T34	0	25060	0	0
T35	0	63854	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714842073	90935	0	0
T24	39931	0	0	0
T30	119250	2568	0	0
T31	0	1193	0	0
T34	0	2526	0	0
T35	0	6339	0	0
T36	14726	0	0	0
T50	0	2630	0	0
T84	274646	0	0	0
T86	0	8714	0	0
T87	0	2630	0	0
T88	0	5604	0	0
T89	0	3253	0	0
T90	0	10187	0	0
T91	162005	0	0	0
T92	5946	0	0	0
T93	39327	0	0	0
T94	245873	0	0	0
T95	35610	0	0	0
T96	335275	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714842073	79287	0	0
T24	39931	0	0	0
T30	119250	2087	0	0
T31	0	1197	0	0
T34	0	2299	0	0
T35	0	5191	0	0
T36	14726	0	0	0
T50	0	2115	0	0
T84	274646	0	0	0
T86	0	7590	0	0
T87	0	2169	0	0
T88	0	5173	0	0
T89	0	2653	0	0
T90	0	9219	0	0
T91	162005	0	0	0
T92	5946	0	0	0
T93	39327	0	0	0
T94	245873	0	0	0
T95	35610	0	0	0
T96	335275	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714842073	79518	0	0
T24	39931	0	0	0
T30	119250	2171	0	0
T31	0	1136	0	0
T34	0	2311	0	0
T35	0	5192	0	0
T36	14726	0	0	0
T50	0	2332	0	0
T84	274646	0	0	0
T86	0	7326	0	0
T87	0	2346	0	0
T88	0	4946	0	0
T89	0	2899	0	0
T90	0	8831	0	0
T91	162005	0	0	0
T92	5946	0	0	0
T93	39327	0	0	0
T94	245873	0	0	0
T95	35610	0	0	0
T96	335275	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714842073	91325	0	0
T24	39931	0	0	0
T30	119250	2483	0	0
T31	0	1268	0	0
T34	0	2435	0	0
T35	0	5994	0	0
T36	14726	0	0	0
T50	0	2709	0	0
T84	274646	0	0	0
T86	0	8711	0	0
T87	0	2553	0	0
T88	0	5642	0	0
T89	0	3542	0	0
T90	0	9852	0	0
T91	162005	0	0	0
T92	5946	0	0	0
T93	39327	0	0	0
T94	245873	0	0	0
T95	35610	0	0	0
T96	335275	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714842073	80202	0	0
T24	39931	0	0	0
T30	119250	2278	0	0
T31	0	1031	0	0
T34	0	2072	0	0
T35	0	5471	0	0
T36	14726	0	0	0
T50	0	2221	0	0
T84	274646	0	0	0
T86	0	7691	0	0
T87	0	2195	0	0
T88	0	5268	0	0
T89	0	2949	0	0
T90	0	8721	0	0
T91	162005	0	0	0
T92	5946	0	0	0
T93	39327	0	0	0
T94	245873	0	0	0
T95	35610	0	0	0
T96	335275	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714842073	89579	0	0
T24	39931	0	0	0
T30	119250	2571	0	0
T31	0	1166	0	0
T34	0	2386	0	0
T35	0	6215	0	0
T36	14726	0	0	0
T50	0	2691	0	0
T84	274646	0	0	0
T86	0	8354	0	0
T87	0	2448	0	0
T88	0	5438	0	0
T89	0	3473	0	0
T90	0	10411	0	0
T91	162005	0	0	0
T92	5946	0	0	0
T93	39327	0	0	0
T94	245873	0	0	0
T95	35610	0	0	0
T96	335275	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714842073	78551	0	0
T24	39931	0	0	0
T30	119250	2259	0	0
T31	0	975	0	0
T34	0	2186	0	0
T35	0	5107	0	0
T36	14726	0	0	0
T50	0	2534	0	0
T84	274646	0	0	0
T86	0	7636	0	0
T87	0	2338	0	0
T88	0	4990	0	0
T89	0	2746	0	0
T90	0	8690	0	0
T91	162005	0	0	0
T92	5946	0	0	0
T93	39327	0	0	0
T94	245873	0	0	0
T95	35610	0	0	0
T96	335275	0	0	0