Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	351103	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4318336	1		T1	10		T2	15		T3	11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1147529	1		T1	1		T2	1		T3	1
values[0x0]	1649767	1		T1	7		T2	8		T3	10
values[0x1]	1872143	1		T1	11		T2	11		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156126	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4513313	1		T1	10		T2	15		T3	14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18310	1		T5	575		T8	953		T15	353
valid_sources[0x01]	19483	1		T5	494		T8	954		T15	352
valid_sources[0x02]	19235	1		T5	487		T8	946		T14	1
valid_sources[0x03]	17290	1		T5	536		T8	1004		T13	9
valid_sources[0x04]	18650	1		T5	549		T8	1017		T15	339
valid_sources[0x05]	18110	1		T5	667		T8	937		T14	7
valid_sources[0x06]	17468	1		T5	541		T8	970		T15	336
valid_sources[0x07]	18961	1		T5	500		T8	990		T15	336
valid_sources[0x08]	18840	1		T3	1		T5	515		T8	1085
valid_sources[0x09]	17227	1		T5	565		T8	1003		T15	370
valid_sources[0x0a]	17056	1		T5	426		T8	885		T12	1
valid_sources[0x0b]	19049	1		T5	557		T8	966		T48	1
valid_sources[0x0c]	18449	1		T5	417		T8	908		T14	4
valid_sources[0x0d]	18969	1		T5	633		T8	1018		T15	340
valid_sources[0x0e]	17064	1		T5	568		T8	952		T15	370
valid_sources[0x0f]	18062	1		T1	1		T2	4		T5	514
valid_sources[0x10]	18795	1		T5	564		T8	1001		T15	346
valid_sources[0x11]	17778	1		T5	569		T8	1016		T14	4
valid_sources[0x12]	18824	1		T5	466		T6	1		T8	915
valid_sources[0x13]	18803	1		T5	732		T8	934		T15	327
valid_sources[0x14]	18005	1		T5	533		T8	973		T15	383
valid_sources[0x15]	18328	1		T5	486		T8	990		T15	363
valid_sources[0x16]	18104	1		T5	635		T8	1089		T14	6
valid_sources[0x17]	17578	1		T5	460		T8	920		T15	323
valid_sources[0x18]	18436	1		T3	2		T5	431		T8	849
valid_sources[0x19]	18388	1		T5	608		T8	961		T13	1
valid_sources[0x1a]	17394	1		T5	375		T8	974		T48	1
valid_sources[0x1b]	17794	1		T5	380		T8	964		T48	1
valid_sources[0x1c]	19625	1		T5	484		T8	1007		T14	1
valid_sources[0x1d]	17902	1		T5	509		T8	1026		T11	1
valid_sources[0x1e]	19513	1		T1	3		T5	479		T8	906
valid_sources[0x1f]	17865	1		T5	633		T8	1030		T14	3
valid_sources[0x20]	17682	1		T5	584		T8	932		T15	351
valid_sources[0x21]	17526	1		T5	456		T8	1014		T14	3
valid_sources[0x22]	17311	1		T5	432		T8	1014		T14	2
valid_sources[0x23]	17609	1		T5	499		T8	904		T13	5
valid_sources[0x24]	18683	1		T5	580		T8	946		T13	7
valid_sources[0x25]	17481	1		T5	420		T8	965		T14	1
valid_sources[0x26]	17757	1		T3	1		T5	475		T8	1031
valid_sources[0x27]	18050	1		T1	1		T5	547		T8	940
valid_sources[0x28]	19147	1		T5	622		T8	986		T10	19
valid_sources[0x29]	19313	1		T3	1		T5	519		T7	1
valid_sources[0x2a]	18150	1		T5	535		T8	1028		T15	347
valid_sources[0x2b]	17997	1		T5	548		T8	986		T15	356
valid_sources[0x2c]	17495	1		T5	457		T6	2		T8	984
valid_sources[0x2d]	18602	1		T3	1		T5	513		T8	960
valid_sources[0x2e]	18233	1		T5	412		T8	1005		T15	388
valid_sources[0x2f]	17969	1		T5	522		T8	943		T15	362
valid_sources[0x30]	17757	1		T5	513		T8	1020		T12	1
valid_sources[0x31]	18484	1		T5	481		T7	3		T8	973
valid_sources[0x32]	19165	1		T5	501		T8	972		T14	4
valid_sources[0x33]	18628	1		T3	1		T5	554		T8	972
valid_sources[0x34]	18155	1		T5	534		T8	966		T13	14
valid_sources[0x35]	19174	1		T5	451		T8	1013		T15	324
valid_sources[0x36]	19316	1		T2	5		T5	570		T8	930
valid_sources[0x37]	19033	1		T5	376		T8	1010		T15	328
valid_sources[0x38]	18899	1		T5	464		T8	1002		T11	1
valid_sources[0x39]	18275	1		T5	430		T8	977		T48	1
valid_sources[0x3a]	18047	1		T5	423		T8	989		T11	1
valid_sources[0x3b]	18873	1		T5	468		T8	992		T15	324
valid_sources[0x3c]	18400	1		T5	478		T8	959		T14	2
valid_sources[0x3d]	19664	1		T5	635		T8	993		T48	2
valid_sources[0x3e]	17598	1		T3	1		T5	564		T8	894
valid_sources[0x3f]	18765	1		T1	1		T5	645		T8	998
valid_sources[0x40]	17314	1		T5	563		T8	896		T15	348
valid_sources[0x41]	17454	1		T5	486		T8	923		T14	1
valid_sources[0x42]	18284	1		T5	530		T8	986		T14	3
valid_sources[0x43]	18806	1		T5	619		T8	944		T48	3
valid_sources[0x44]	18378	1		T5	594		T8	880		T15	351
valid_sources[0x45]	18985	1		T5	499		T8	1011		T11	1
valid_sources[0x46]	19176	1		T5	619		T8	1017		T15	345
valid_sources[0x47]	18715	1		T5	712		T6	1		T8	971
valid_sources[0x48]	17864	1		T5	595		T8	961		T15	381
valid_sources[0x49]	19105	1		T5	686		T8	913		T48	1
valid_sources[0x4a]	17604	1		T5	528		T8	894		T13	10
valid_sources[0x4b]	17431	1		T5	475		T6	1		T8	927
valid_sources[0x4c]	19663	1		T5	442		T8	922		T11	1
valid_sources[0x4d]	17887	1		T3	1		T5	419		T6	1
valid_sources[0x4e]	17535	1		T5	418		T8	997		T12	1
valid_sources[0x4f]	18158	1		T5	505		T8	915		T14	5
valid_sources[0x50]	18514	1		T1	1		T5	623		T8	891
valid_sources[0x51]	19308	1		T5	552		T8	952		T15	313
valid_sources[0x52]	18141	1		T5	468		T8	976		T15	370
valid_sources[0x53]	17182	1		T5	492		T8	868		T14	2
valid_sources[0x54]	20090	1		T5	729		T8	966		T14	4
valid_sources[0x55]	17900	1		T3	1		T5	643		T8	903
valid_sources[0x56]	17441	1		T5	473		T8	937		T15	339
valid_sources[0x57]	19879	1		T5	602		T8	965		T13	16
valid_sources[0x58]	18017	1		T5	433		T8	941		T14	1
valid_sources[0x59]	19525	1		T5	506		T8	1013		T14	2
valid_sources[0x5a]	16970	1		T5	557		T8	990		T12	1
valid_sources[0x5b]	17662	1		T5	677		T8	907		T11	2
valid_sources[0x5c]	18493	1		T1	1		T3	1		T5	456
valid_sources[0x5d]	17451	1		T5	497		T8	885		T11	1
valid_sources[0x5e]	17357	1		T5	338		T8	1026		T15	337
valid_sources[0x5f]	16972	1		T5	364		T8	1022		T15	378
valid_sources[0x60]	16861	1		T5	382		T8	1013		T14	4
valid_sources[0x61]	18032	1		T5	473		T8	960		T15	352
valid_sources[0x62]	17613	1		T5	449		T8	1028		T15	356
valid_sources[0x63]	18465	1		T3	1		T5	575		T8	956
valid_sources[0x64]	19347	1		T5	557		T8	999		T14	4
valid_sources[0x65]	17918	1		T5	451		T8	968		T15	341
valid_sources[0x66]	16365	1		T5	549		T8	970		T15	381
valid_sources[0x67]	19141	1		T5	497		T8	905		T14	1
valid_sources[0x68]	17331	1		T5	498		T8	992		T14	2
valid_sources[0x69]	18294	1		T5	533		T8	873		T12	1
valid_sources[0x6a]	17500	1		T5	512		T6	1		T8	937
valid_sources[0x6b]	18095	1		T5	730		T8	970		T14	9
valid_sources[0x6c]	17706	1		T5	482		T8	947		T12	1
valid_sources[0x6d]	17890	1		T5	609		T8	991		T14	2
valid_sources[0x6e]	16955	1		T3	1		T5	367		T8	997
valid_sources[0x6f]	16302	1		T5	606		T8	926		T15	307
valid_sources[0x70]	18610	1		T5	603		T8	953		T14	1
valid_sources[0x71]	17965	1		T4	2		T5	595		T8	960
valid_sources[0x72]	19784	1		T5	804		T8	995		T48	2
valid_sources[0x73]	18624	1		T1	2		T5	575		T8	973
valid_sources[0x74]	17827	1		T5	502		T7	3		T8	944
valid_sources[0x75]	17742	1		T4	1		T5	481		T7	4
valid_sources[0x76]	18878	1		T5	431		T8	906		T14	12
valid_sources[0x77]	20413	1		T5	474		T8	986		T14	8
valid_sources[0x78]	17357	1		T5	518		T8	961		T15	343
valid_sources[0x79]	17392	1		T5	662		T8	973		T15	336
valid_sources[0x7a]	18405	1		T5	538		T8	931		T15	303
valid_sources[0x7b]	18522	1		T5	420		T8	1000		T14	5
valid_sources[0x7c]	19306	1		T5	435		T8	964		T14	5
valid_sources[0x7d]	19492	1		T3	1		T5	501		T8	914
valid_sources[0x7e]	19703	1		T5	564		T8	984		T14	4
valid_sources[0x7f]	18826	1		T5	415		T8	1003		T14	3
valid_sources[0x80]	18631	1		T5	458		T8	972		T15	305

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1076935

1

T2

1

T5

31148

T7

1

values[0x0]

all_enables

biggest_size

1620176

1

T1

3

T2

6

T3

8

values[0x1]

all_enables

biggest_size

1621225

1

T1

7

T2

8

T3

3