Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	865148441	5082580	0	0
wdog_bark_thold_rd_A	865148441	96218	0	0
wdog_bite_thold_rd_A	865148441	84615	0	0
wdog_ctrl_rd_A	865148441	85258	0	0
wdog_regwen_rd_A	865148441	95193	0	0
wkup_ctrl_rd_A	865148441	83593	0	0
wkup_thold_hi_rd_A	865148441	96466	0	0
wkup_thold_lo_rd_A	865148441	83797	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	865148441	5082580	0	0
T5	414549	151157	0	0
T6	26908	0	0	0
T7	3530	0	0	0
T8	747969	268653	0	0
T9	8224	0	0	0
T10	18062	0	0	0
T11	139307	0	0	0
T12	320527	0	0	0
T13	590472	0	0	0
T15	0	102926	0	0
T33	0	53888	0	0
T34	0	172373	0	0
T43	0	15881	0	0
T44	0	102690	0	0
T45	0	77531	0	0
T46	0	63618	0	0
T47	0	70224	0	0
T48	42971	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	865148441	96218	0	0
T26	0	3522	0	0
T33	217663	0	0	0
T34	637306	0	0	0
T44	478502	10364	0	0
T45	219538	0	0	0
T53	238391	0	0	0
T54	6961	0	0	0
T55	3838	0	0	0
T56	982819	0	0	0
T61	0	4624	0	0
T73	0	5867	0	0
T74	0	8287	0	0
T94	0	25749	0	0
T95	0	7328	0	0
T96	0	8805	0	0
T97	0	2448	0	0
T98	0	6562	0	0
T99	54851	0	0	0
T100	19218	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	865148441	84615	0	0
T26	0	3123	0	0
T33	217663	0	0	0
T34	637306	0	0	0
T44	478502	8553	0	0
T45	219538	0	0	0
T53	238391	0	0	0
T54	6961	0	0	0
T55	3838	0	0	0
T56	982819	0	0	0
T61	0	4155	0	0
T73	0	4974	0	0
T74	0	7253	0	0
T94	0	22973	0	0
T95	0	6470	0	0
T96	0	7798	0	0
T97	0	2314	0	0
T98	0	5757	0	0
T99	54851	0	0	0
T100	19218	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	865148441	85258	0	0
T26	0	3197	0	0
T33	217663	0	0	0
T34	637306	0	0	0
T44	478502	9090	0	0
T45	219538	0	0	0
T53	238391	0	0	0
T54	6961	0	0	0
T55	3838	0	0	0
T56	982819	0	0	0
T61	0	4108	0	0
T73	0	4725	0	0
T74	0	7203	0	0
T94	0	22754	0	0
T95	0	6372	0	0
T96	0	7346	0	0
T97	0	2601	0	0
T98	0	6340	0	0
T99	54851	0	0	0
T100	19218	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	865148441	95193	0	0
T26	0	3763	0	0
T33	217663	0	0	0
T34	637306	0	0	0
T44	478502	9976	0	0
T45	219538	0	0	0
T53	238391	0	0	0
T54	6961	0	0	0
T55	3838	0	0	0
T56	982819	0	0	0
T61	0	4704	0	0
T73	0	5580	0	0
T74	0	8145	0	0
T94	0	25503	0	0
T95	0	6904	0	0
T96	0	8361	0	0
T97	0	2565	0	0
T98	0	6647	0	0
T99	54851	0	0	0
T100	19218	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	865148441	83593	0	0
T26	0	3174	0	0
T33	217663	0	0	0
T34	637306	0	0	0
T44	478502	8448	0	0
T45	219538	0	0	0
T53	238391	0	0	0
T54	6961	0	0	0
T55	3838	0	0	0
T56	982819	0	0	0
T61	0	4005	0	0
T73	0	4696	0	0
T74	0	7417	0	0
T94	0	22650	0	0
T95	0	6057	0	0
T96	0	8024	0	0
T97	0	2284	0	0
T98	0	5780	0	0
T99	54851	0	0	0
T100	19218	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	865148441	96466	0	0
T26	0	3487	0	0
T33	217663	0	0	0
T34	637306	0	0	0
T44	478502	10121	0	0
T45	219538	0	0	0
T53	238391	0	0	0
T54	6961	0	0	0
T55	3838	0	0	0
T56	982819	0	0	0
T61	0	4614	0	0
T73	0	5879	0	0
T74	0	8393	0	0
T94	0	25612	0	0
T95	0	7204	0	0
T96	0	8960	0	0
T97	0	2742	0	0
T98	0	6803	0	0
T99	54851	0	0	0
T100	19218	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	865148441	83797	0	0
T26	0	3024	0	0
T33	217663	0	0	0
T34	637306	0	0	0
T44	478502	8684	0	0
T45	219538	0	0	0
T53	238391	0	0	0
T54	6961	0	0	0
T55	3838	0	0	0
T56	982819	0	0	0
T61	0	3916	0	0
T73	0	5261	0	0
T74	0	7582	0	0
T94	0	22864	0	0
T95	0	6175	0	0
T96	0	7434	0	0
T97	0	2410	0	0
T98	0	5650	0	0
T99	54851	0	0	0
T100	19218	0	0	0