Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	337179	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4143859	1		T1	13		T2	203		T3	13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1102347	1		T1	1		T2	59		T3	1
values[0x0]	1585266	1		T1	9		T2	132		T3	9
values[0x1]	1793425	1		T1	8		T2	132		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151249	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4329789	1		T1	13		T2	234		T3	13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18004	1		T2	1		T5	188		T15	197
valid_sources[0x01]	17023	1		T5	187		T14	3		T15	233
valid_sources[0x02]	17471	1		T5	146		T15	281		T35	1
valid_sources[0x03]	16846	1		T5	185		T13	1		T14	1
valid_sources[0x04]	16406	1		T3	1		T5	178		T14	3
valid_sources[0x05]	17421	1		T5	184		T14	2		T15	254
valid_sources[0x06]	17114	1		T5	170		T15	243		T34	3
valid_sources[0x07]	16111	1		T3	1		T5	169		T7	1
valid_sources[0x08]	16512	1		T5	174		T7	1		T14	4
valid_sources[0x09]	18587	1		T5	166		T7	1		T15	251
valid_sources[0x0a]	19824	1		T5	165		T14	3		T15	275
valid_sources[0x0b]	18867	1		T5	171		T14	9		T15	266
valid_sources[0x0c]	16298	1		T5	156		T7	1		T14	4
valid_sources[0x0d]	16050	1		T5	186		T13	1		T15	288
valid_sources[0x0e]	16378	1		T5	158		T13	1		T15	251
valid_sources[0x0f]	18037	1		T5	170		T14	2		T15	236
valid_sources[0x10]	16341	1		T2	7		T3	1		T5	186
valid_sources[0x11]	17948	1		T2	1		T3	1		T5	174
valid_sources[0x12]	18889	1		T3	1		T5	160		T15	241
valid_sources[0x13]	17570	1		T5	215		T14	1		T15	237
valid_sources[0x14]	16957	1		T5	197		T15	269		T35	5
valid_sources[0x15]	17984	1		T3	1		T5	180		T14	5
valid_sources[0x16]	17849	1		T5	213		T7	1		T15	282
valid_sources[0x17]	17406	1		T5	157		T15	234		T34	4
valid_sources[0x18]	17512	1		T1	18		T5	194		T14	1
valid_sources[0x19]	17561	1		T2	6		T5	180		T14	3
valid_sources[0x1a]	18692	1		T5	212		T9	2		T14	1
valid_sources[0x1b]	17000	1		T2	1		T4	1		T5	193
valid_sources[0x1c]	17317	1		T3	1		T5	169		T14	2
valid_sources[0x1d]	18419	1		T5	191		T14	2		T15	259
valid_sources[0x1e]	16513	1		T5	173		T14	2		T15	285
valid_sources[0x1f]	17846	1		T5	149		T15	214		T35	1
valid_sources[0x20]	18367	1		T5	148		T7	1		T12	2
valid_sources[0x21]	17390	1		T2	7		T5	153		T14	3
valid_sources[0x22]	17347	1		T5	168		T7	1		T12	1
valid_sources[0x23]	17519	1		T2	1		T5	168		T15	250
valid_sources[0x24]	17885	1		T3	1		T5	185		T15	225
valid_sources[0x25]	18681	1		T2	4		T5	168		T14	1
valid_sources[0x26]	17101	1		T5	154		T6	2		T14	1
valid_sources[0x27]	16638	1		T5	165		T14	1		T15	260
valid_sources[0x28]	17313	1		T5	157		T14	4		T15	226
valid_sources[0x29]	17474	1		T2	9		T5	167		T14	1
valid_sources[0x2a]	18286	1		T2	8		T5	198		T14	1
valid_sources[0x2b]	18875	1		T5	191		T7	2		T15	253
valid_sources[0x2c]	17482	1		T2	3		T5	183		T14	3
valid_sources[0x2d]	17460	1		T5	179		T14	5		T15	272
valid_sources[0x2e]	18230	1		T5	137		T14	1		T15	221
valid_sources[0x2f]	17129	1		T5	186		T11	1		T14	2
valid_sources[0x30]	16918	1		T2	7		T5	187		T14	3
valid_sources[0x31]	16858	1		T5	203		T14	4		T15	226
valid_sources[0x32]	18089	1		T5	155		T6	3		T14	1
valid_sources[0x33]	16099	1		T5	171		T14	1		T15	237
valid_sources[0x34]	17825	1		T5	184		T7	1		T15	246
valid_sources[0x35]	16776	1		T5	175		T14	1		T15	210
valid_sources[0x36]	16389	1		T2	2		T5	192		T15	189
valid_sources[0x37]	16705	1		T5	180		T6	1		T14	2
valid_sources[0x38]	18243	1		T5	214		T15	205		T35	1
valid_sources[0x39]	17041	1		T5	190		T6	2		T15	241
valid_sources[0x3a]	17491	1		T5	172		T15	248		T35	2
valid_sources[0x3b]	17307	1		T5	157		T14	4		T15	238
valid_sources[0x3c]	17813	1		T5	182		T8	2		T15	213
valid_sources[0x3d]	17430	1		T5	157		T7	1		T14	1
valid_sources[0x3e]	18879	1		T5	193		T14	2		T15	270
valid_sources[0x3f]	17077	1		T5	172		T15	280		T34	2
valid_sources[0x40]	18986	1		T5	197		T15	309		T19	916
valid_sources[0x41]	16899	1		T5	190		T14	2		T15	219
valid_sources[0x42]	18451	1		T5	158		T6	1		T15	222
valid_sources[0x43]	16689	1		T5	179		T15	268		T35	1
valid_sources[0x44]	16433	1		T5	197		T15	282		T19	325
valid_sources[0x45]	18051	1		T2	5		T5	193		T15	274
valid_sources[0x46]	16983	1		T3	2		T5	173		T15	247
valid_sources[0x47]	17300	1		T2	8		T5	174		T14	2
valid_sources[0x48]	17407	1		T5	178		T15	245		T35	2
valid_sources[0x49]	18688	1		T5	189		T14	1		T15	247
valid_sources[0x4a]	17246	1		T5	179		T14	2		T15	280
valid_sources[0x4b]	18131	1		T5	154		T14	1		T15	241
valid_sources[0x4c]	18265	1		T5	167		T14	1		T15	243
valid_sources[0x4d]	17064	1		T5	190		T15	206		T105	1
valid_sources[0x4e]	17846	1		T5	208		T14	5		T15	237
valid_sources[0x4f]	17926	1		T5	174		T14	2		T15	295
valid_sources[0x50]	15886	1		T5	186		T15	222		T19	390
valid_sources[0x51]	17701	1		T5	185		T10	19		T14	2
valid_sources[0x52]	18096	1		T5	160		T14	1		T15	230
valid_sources[0x53]	16712	1		T5	209		T7	1		T14	1
valid_sources[0x54]	16135	1		T5	165		T13	1		T14	1
valid_sources[0x55]	17440	1		T5	157		T9	1		T14	1
valid_sources[0x56]	17054	1		T5	198		T13	1		T15	246
valid_sources[0x57]	18350	1		T2	11		T5	185		T14	3
valid_sources[0x58]	16948	1		T5	215		T15	256		T34	7
valid_sources[0x59]	16545	1		T5	195		T14	1		T15	274
valid_sources[0x5a]	17906	1		T5	192		T15	220		T35	4
valid_sources[0x5b]	17755	1		T3	1		T5	174		T15	244
valid_sources[0x5c]	17292	1		T5	169		T14	1		T15	243
valid_sources[0x5d]	17420	1		T5	176		T9	5		T13	1
valid_sources[0x5e]	16947	1		T5	177		T14	3		T15	275
valid_sources[0x5f]	17995	1		T5	194		T7	1		T15	260
valid_sources[0x60]	16837	1		T5	177		T12	2		T15	310
valid_sources[0x61]	18179	1		T5	176		T15	235		T19	419
valid_sources[0x62]	18069	1		T5	184		T15	276		T34	6
valid_sources[0x63]	18729	1		T5	196		T15	244		T35	6
valid_sources[0x64]	18288	1		T5	180		T15	231		T35	2
valid_sources[0x65]	17729	1		T2	9		T5	174		T14	2
valid_sources[0x66]	17230	1		T3	1		T5	194		T8	1
valid_sources[0x67]	17622	1		T5	187		T15	254		T35	4
valid_sources[0x68]	17054	1		T5	171		T9	1		T15	305
valid_sources[0x69]	17474	1		T5	167		T15	265		T35	2
valid_sources[0x6a]	17591	1		T5	163		T14	2		T15	233
valid_sources[0x6b]	17235	1		T5	137		T9	1		T12	3
valid_sources[0x6c]	17939	1		T5	179		T13	1		T15	240
valid_sources[0x6d]	17245	1		T5	188		T14	1		T15	201
valid_sources[0x6e]	17840	1		T5	178		T14	2		T15	254
valid_sources[0x6f]	17574	1		T5	176		T14	1		T15	257
valid_sources[0x70]	15913	1		T5	164		T15	198		T19	565
valid_sources[0x71]	17519	1		T2	4		T5	162		T14	1
valid_sources[0x72]	17420	1		T5	200		T6	4		T14	1
valid_sources[0x73]	17833	1		T2	25		T5	200		T15	257
valid_sources[0x74]	17342	1		T5	186		T14	2		T15	210
valid_sources[0x75]	18074	1		T5	179		T14	1		T15	280
valid_sources[0x76]	17304	1		T5	176		T15	277		T34	4
valid_sources[0x77]	16589	1		T5	188		T11	2		T15	253
valid_sources[0x78]	18288	1		T2	23		T5	182		T15	264
valid_sources[0x79]	18928	1		T5	175		T11	5		T15	262
valid_sources[0x7a]	17574	1		T5	156		T15	206		T35	2
valid_sources[0x7b]	17860	1		T5	187		T14	1		T15	245
valid_sources[0x7c]	17625	1		T5	167		T15	213		T34	13
valid_sources[0x7d]	17163	1		T2	9		T5	144		T14	1
valid_sources[0x7e]	18622	1		T5	163		T14	1		T15	245
valid_sources[0x7f]	17343	1		T2	6		T5	164		T15	283
valid_sources[0x80]	17303	1		T5	179		T15	257		T19	490

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1033242

1

T1

1

T2

27

T3

1

values[0x0]

all_enables

biggest_size

1556357

1

T1

6

T2

89

T3

7

values[0x1]

all_enables

biggest_size

1554260

1

T1

6

T2

87

T3

5