Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	947928107	4870751	0	0
wdog_bark_thold_rd_A	947928107	149341	0	0
wdog_bite_thold_rd_A	947928107	130211	0	0
wdog_ctrl_rd_A	947928107	131014	0	0
wdog_regwen_rd_A	947928107	148509	0	0
wkup_ctrl_rd_A	947928107	131046	0	0
wkup_thold_hi_rd_A	947928107	149940	0	0
wkup_thold_lo_rd_A	947928107	129920	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947928107	4870751	0	0
T5	188124	52072	0	0
T6	18468	0	0	0
T7	50843	0	0	0
T8	54151	0	0	0
T9	910607	0	0	0
T10	27685	0	0	0
T11	845673	0	0	0
T12	48243	0	0	0
T13	96767	0	0	0
T15	0	67624	0	0
T17	13682	0	0	0
T19	0	174353	0	0
T36	0	162805	0	0
T45	0	116723	0	0
T46	0	109269	0	0
T47	0	198236	0	0
T48	0	152004	0	0
T49	0	82664	0	0
T50	0	74702	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947928107	149341	0	0
T15	298798	3896	0	0
T16	139876	0	0	0
T19	693038	9137	0	0
T34	331728	0	0	0
T35	110346	0	0	0
T36	100000	0	0	0
T45	0	11837	0	0
T47	0	10194	0	0
T48	0	15062	0	0
T50	0	3848	0	0
T51	0	8769	0	0
T90	104614	0	0	0
T102	0	3698	0	0
T103	0	13419	0	0
T104	0	9382	0	0
T105	55621	0	0	0
T106	115875	0	0	0
T107	945231	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947928107	130211	0	0
T15	298798	3506	0	0
T16	139876	0	0	0
T19	693038	7763	0	0
T34	331728	0	0	0
T35	110346	0	0	0
T36	100000	0	0	0
T45	0	10465	0	0
T47	0	9106	0	0
T48	0	12973	0	0
T50	0	3176	0	0
T51	0	7846	0	0
T90	104614	0	0	0
T102	0	3209	0	0
T103	0	11551	0	0
T104	0	8690	0	0
T105	55621	0	0	0
T106	115875	0	0	0
T107	945231	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947928107	131014	0	0
T15	298798	3315	0	0
T16	139876	0	0	0
T19	693038	7838	0	0
T34	331728	0	0	0
T35	110346	0	0	0
T36	100000	0	0	0
T45	0	10323	0	0
T47	0	9412	0	0
T48	0	13161	0	0
T50	0	3143	0	0
T51	0	7663	0	0
T90	104614	0	0	0
T102	0	3447	0	0
T103	0	11460	0	0
T104	0	8531	0	0
T105	55621	0	0	0
T106	115875	0	0	0
T107	945231	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947928107	148509	0	0
T15	298798	3877	0	0
T16	139876	0	0	0
T19	693038	9055	0	0
T34	331728	0	0	0
T35	110346	0	0	0
T36	100000	0	0	0
T45	0	11163	0	0
T47	0	10698	0	0
T48	0	14722	0	0
T50	0	3571	0	0
T51	0	8578	0	0
T90	104614	0	0	0
T102	0	3666	0	0
T103	0	13532	0	0
T104	0	9689	0	0
T105	55621	0	0	0
T106	115875	0	0	0
T107	945231	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947928107	131046	0	0
T15	298798	3244	0	0
T16	139876	0	0	0
T19	693038	8016	0	0
T34	331728	0	0	0
T35	110346	0	0	0
T36	100000	0	0	0
T45	0	10024	0	0
T47	0	9598	0	0
T48	0	13353	0	0
T50	0	3156	0	0
T51	0	8004	0	0
T90	104614	0	0	0
T102	0	3411	0	0
T103	0	11463	0	0
T104	0	8387	0	0
T105	55621	0	0	0
T106	115875	0	0	0
T107	945231	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947928107	149940	0	0
T15	298798	3839	0	0
T16	139876	0	0	0
T19	693038	8865	0	0
T34	331728	0	0	0
T35	110346	0	0	0
T36	100000	0	0	0
T45	0	11666	0	0
T47	0	10600	0	0
T48	0	15020	0	0
T50	0	3497	0	0
T51	0	8814	0	0
T90	104614	0	0	0
T102	0	3763	0	0
T103	0	13608	0	0
T104	0	9229	0	0
T105	55621	0	0	0
T106	115875	0	0	0
T107	945231	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947928107	129920	0	0
T15	298798	3538	0	0
T16	139876	0	0	0
T19	693038	7417	0	0
T34	331728	0	0	0
T35	110346	0	0	0
T36	100000	0	0	0
T45	0	10088	0	0
T47	0	9545	0	0
T48	0	12995	0	0
T50	0	3108	0	0
T51	0	7882	0	0
T90	104614	0	0	0
T102	0	3464	0	0
T103	0	11426	0	0
T104	0	8144	0	0
T105	55621	0	0	0
T106	115875	0	0	0
T107	945231	0	0	0