Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	413614	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5160664	1		T1	232		T2	22556		T3	14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1369965	1		T1	26		T2	6145		T3	1
values[0x0]	1970745	1		T1	140		T2	8515		T3	11
values[0x1]	2233568	1		T1	155		T2	9888		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	182169	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5392109	1		T1	247		T2	23646		T3	17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22375	1		T2	120		T5	223		T6	434
valid_sources[0x01]	21333	1		T1	10		T2	102		T4	1
valid_sources[0x02]	21314	1		T2	97		T5	193		T6	467
valid_sources[0x03]	21679	1		T2	104		T5	207		T6	424
valid_sources[0x04]	21150	1		T2	77		T5	211		T6	439
valid_sources[0x05]	20144	1		T2	88		T5	173		T6	442
valid_sources[0x06]	20762	1		T2	96		T5	245		T6	419
valid_sources[0x07]	22500	1		T2	89		T4	1		T5	187
valid_sources[0x08]	22791	1		T1	1		T2	82		T5	216
valid_sources[0x09]	21408	1		T2	103		T5	218		T6	385
valid_sources[0x0a]	22592	1		T1	3		T2	87		T5	183
valid_sources[0x0b]	22994	1		T1	1		T2	113		T5	192
valid_sources[0x0c]	22461	1		T1	7		T2	76		T5	197
valid_sources[0x0d]	20921	1		T2	87		T5	236		T6	455
valid_sources[0x0e]	22309	1		T2	97		T5	170		T6	424
valid_sources[0x0f]	23376	1		T2	99		T5	203		T6	449
valid_sources[0x10]	22972	1		T2	97		T5	255		T6	541
valid_sources[0x11]	21510	1		T1	6		T2	70		T5	178
valid_sources[0x12]	21643	1		T2	85		T5	203		T6	451
valid_sources[0x13]	22373	1		T1	2		T2	92		T5	194
valid_sources[0x14]	23561	1		T2	88		T5	166		T6	406
valid_sources[0x15]	21032	1		T2	81		T5	217		T6	455
valid_sources[0x16]	21316	1		T1	2		T2	84		T5	209
valid_sources[0x17]	21274	1		T2	83		T5	224		T6	423
valid_sources[0x18]	21083	1		T2	95		T5	201		T6	463
valid_sources[0x19]	20816	1		T1	4		T2	113		T5	196
valid_sources[0x1a]	21661	1		T2	75		T5	209		T6	459
valid_sources[0x1b]	22827	1		T1	2		T2	73		T5	184
valid_sources[0x1c]	23927	1		T2	93		T5	206		T6	468
valid_sources[0x1d]	23573	1		T1	7		T2	84		T5	220
valid_sources[0x1e]	21369	1		T2	87		T5	192		T6	481
valid_sources[0x1f]	20809	1		T2	102		T5	212		T6	472
valid_sources[0x20]	22360	1		T2	84		T5	210		T6	467
valid_sources[0x21]	22412	1		T2	96		T5	183		T6	412
valid_sources[0x22]	20850	1		T1	1		T2	96		T5	186
valid_sources[0x23]	22702	1		T2	115		T5	192		T6	425
valid_sources[0x24]	19919	1		T1	1		T2	75		T5	232
valid_sources[0x25]	22827	1		T2	86		T5	174		T6	449
valid_sources[0x26]	20799	1		T2	82		T5	238		T6	421
valid_sources[0x27]	22211	1		T1	4		T2	92		T5	212
valid_sources[0x28]	20990	1		T1	1		T2	82		T5	253
valid_sources[0x29]	21373	1		T2	105		T5	206		T6	453
valid_sources[0x2a]	20886	1		T2	107		T5	178		T6	418
valid_sources[0x2b]	21624	1		T2	101		T5	203		T6	480
valid_sources[0x2c]	20877	1		T2	98		T4	1		T5	202
valid_sources[0x2d]	21005	1		T2	121		T5	195		T6	516
valid_sources[0x2e]	21369	1		T2	103		T5	223		T6	466
valid_sources[0x2f]	20245	1		T2	93		T5	201		T6	429
valid_sources[0x30]	21673	1		T2	86		T5	210		T6	439
valid_sources[0x31]	21853	1		T2	87		T5	206		T6	457
valid_sources[0x32]	21850	1		T1	2		T2	97		T5	244
valid_sources[0x33]	22225	1		T1	9		T2	105		T5	224
valid_sources[0x34]	20943	1		T1	2		T2	119		T5	213
valid_sources[0x35]	21187	1		T2	93		T5	193		T6	468
valid_sources[0x36]	21277	1		T2	104		T5	187		T6	435
valid_sources[0x37]	20333	1		T2	85		T5	223		T6	475
valid_sources[0x38]	20477	1		T2	101		T4	1		T5	219
valid_sources[0x39]	21221	1		T2	79		T4	1		T5	236
valid_sources[0x3a]	21720	1		T2	103		T5	221		T6	445
valid_sources[0x3b]	21746	1		T2	74		T5	203		T6	450
valid_sources[0x3c]	23597	1		T1	5		T2	81		T5	239
valid_sources[0x3d]	21349	1		T1	8		T2	84		T5	198
valid_sources[0x3e]	21811	1		T2	100		T5	204		T6	482
valid_sources[0x3f]	22161	1		T2	94		T5	209		T6	448
valid_sources[0x40]	23974	1		T1	3		T2	96		T5	204
valid_sources[0x41]	21897	1		T2	109		T4	1		T5	204
valid_sources[0x42]	22517	1		T2	103		T5	240		T6	500
valid_sources[0x43]	21948	1		T2	100		T5	241		T6	448
valid_sources[0x44]	21317	1		T1	1		T2	116		T5	171
valid_sources[0x45]	20224	1		T2	121		T5	232		T6	469
valid_sources[0x46]	23218	1		T2	95		T5	229		T6	457
valid_sources[0x47]	21581	1		T2	96		T5	188		T6	478
valid_sources[0x48]	22491	1		T2	91		T5	205		T6	477
valid_sources[0x49]	22548	1		T1	2		T2	91		T5	213
valid_sources[0x4a]	21009	1		T1	1		T2	100		T5	248
valid_sources[0x4b]	23528	1		T2	95		T5	248		T6	419
valid_sources[0x4c]	22816	1		T2	101		T4	1		T5	194
valid_sources[0x4d]	22106	1		T1	4		T2	90		T5	210
valid_sources[0x4e]	22712	1		T2	80		T5	246		T6	433
valid_sources[0x4f]	21671	1		T2	109		T5	177		T6	486
valid_sources[0x50]	20476	1		T1	4		T2	87		T5	214
valid_sources[0x51]	22491	1		T2	99		T5	188		T6	487
valid_sources[0x52]	21924	1		T1	4		T2	99		T5	215
valid_sources[0x53]	21117	1		T2	104		T4	1		T5	189
valid_sources[0x54]	20895	1		T1	1		T2	112		T5	219
valid_sources[0x55]	21640	1		T2	97		T5	186		T6	442
valid_sources[0x56]	21601	1		T2	91		T5	205		T6	466
valid_sources[0x57]	21245	1		T1	2		T2	92		T5	222
valid_sources[0x58]	21244	1		T1	1		T2	84		T5	202
valid_sources[0x59]	22241	1		T1	2		T2	101		T5	188
valid_sources[0x5a]	21718	1		T2	105		T4	1		T5	195
valid_sources[0x5b]	21713	1		T2	72		T5	237		T6	501
valid_sources[0x5c]	21795	1		T1	3		T2	107		T5	218
valid_sources[0x5d]	21229	1		T2	110		T5	189		T6	467
valid_sources[0x5e]	21691	1		T2	109		T5	200		T6	447
valid_sources[0x5f]	22333	1		T2	98		T4	2		T5	223
valid_sources[0x60]	22543	1		T2	97		T4	1		T5	203
valid_sources[0x61]	21505	1		T2	98		T5	197		T6	443
valid_sources[0x62]	23667	1		T2	93		T5	217		T6	497
valid_sources[0x63]	20847	1		T1	4		T2	78		T5	184
valid_sources[0x64]	21197	1		T1	7		T2	108		T5	248
valid_sources[0x65]	20939	1		T2	123		T5	247		T6	488
valid_sources[0x66]	20959	1		T1	8		T2	111		T5	234
valid_sources[0x67]	21004	1		T2	95		T5	255		T6	419
valid_sources[0x68]	22449	1		T1	4		T2	83		T5	204
valid_sources[0x69]	21624	1		T2	84		T5	233		T6	465
valid_sources[0x6a]	22730	1		T1	3		T2	103		T5	236
valid_sources[0x6b]	20869	1		T2	94		T5	173		T6	418
valid_sources[0x6c]	21869	1		T2	80		T5	183		T6	494
valid_sources[0x6d]	21327	1		T2	104		T4	1		T5	210
valid_sources[0x6e]	21668	1		T2	92		T5	179		T6	486
valid_sources[0x6f]	23129	1		T2	115		T5	195		T6	479
valid_sources[0x70]	23367	1		T2	104		T5	191		T6	518
valid_sources[0x71]	21849	1		T1	3		T2	94		T5	163
valid_sources[0x72]	22053	1		T2	75		T5	196		T6	433
valid_sources[0x73]	21763	1		T1	5		T2	92		T5	204
valid_sources[0x74]	20378	1		T2	86		T5	175		T6	421
valid_sources[0x75]	21312	1		T2	103		T5	211		T6	475
valid_sources[0x76]	21663	1		T1	6		T2	104		T5	264
valid_sources[0x77]	22208	1		T1	1		T2	106		T5	164
valid_sources[0x78]	23721	1		T1	3		T2	75		T5	222
valid_sources[0x79]	21955	1		T2	101		T5	196		T6	439
valid_sources[0x7a]	21619	1		T1	6		T2	110		T5	184
valid_sources[0x7b]	21767	1		T2	87		T5	207		T6	479
valid_sources[0x7c]	23967	1		T1	3		T2	85		T5	219
valid_sources[0x7d]	21662	1		T1	2		T2	105		T5	218
valid_sources[0x7e]	21940	1		T2	96		T5	203		T6	468
valid_sources[0x7f]	22174	1		T1	10		T2	89		T5	202
valid_sources[0x80]	20505	1		T2	78		T5	178		T6	463

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1287676

1

T1

12

T2

5720

T4

1

values[0x0]

all_enables

biggest_size

1936973

1

T1

104

T2

8375

T3

8

values[0x1]

all_enables

biggest_size

1936015

1

T1

116

T2

8461

T3

6