Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	807406787	6072045	0	0
wdog_bark_thold_rd_A	807406787	105721	0	0
wdog_bite_thold_rd_A	807406787	93173	0	0
wdog_ctrl_rd_A	807406787	91742	0	0
wdog_regwen_rd_A	807406787	106056	0	0
wkup_ctrl_rd_A	807406787	92422	0	0
wkup_thold_hi_rd_A	807406787	105001	0	0
wkup_thold_lo_rd_A	807406787	91858	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	807406787	6072045	0	0
T2	107150	29353	0	0
T3	185561	0	0	0
T4	23260	0	0	0
T5	258111	57011	0	0
T6	504483	130826	0	0
T7	6472	0	0	0
T8	646184	95511	0	0
T9	12427	0	0	0
T10	103663	0	0	0
T12	52080	0	0	0
T31	0	66438	0	0
T40	0	173029	0	0
T41	0	99871	0	0
T42	0	57355	0	0
T43	0	62361	0	0
T44	0	20956	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	807406787	105721	0	0
T5	258111	6200	0	0
T6	504483	0	0	0
T7	6472	0	0	0
T8	646184	0	0	0
T9	12427	0	0	0
T10	103663	0	0	0
T11	7760	0	0	0
T12	52080	0	0	0
T40	0	17880	0	0
T42	0	5758	0	0
T43	0	6444	0	0
T44	0	2198	0	0
T45	512687	0	0	0
T91	2567	0	0	0
T92	0	12040	0	0
T93	0	10570	0	0
T94	0	2912	0	0
T95	0	1095	0	0
T96	0	10759	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	807406787	93173	0	0
T5	258111	5095	0	0
T6	504483	0	0	0
T7	6472	0	0	0
T8	646184	0	0	0
T9	12427	0	0	0
T10	103663	0	0	0
T11	7760	0	0	0
T12	52080	0	0	0
T40	0	15802	0	0
T42	0	4799	0	0
T43	0	5440	0	0
T44	0	1773	0	0
T45	512687	0	0	0
T91	2567	0	0	0
T92	0	10911	0	0
T93	0	9325	0	0
T94	0	2833	0	0
T95	0	890	0	0
T96	0	9613	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	807406787	91742	0	0
T5	258111	5228	0	0
T6	504483	0	0	0
T7	6472	0	0	0
T8	646184	0	0	0
T9	12427	0	0	0
T10	103663	0	0	0
T11	7760	0	0	0
T12	52080	0	0	0
T40	0	15058	0	0
T42	0	5019	0	0
T43	0	5254	0	0
T44	0	1865	0	0
T45	512687	0	0	0
T91	2567	0	0	0
T92	0	10346	0	0
T93	0	9287	0	0
T94	0	2779	0	0
T95	0	863	0	0
T96	0	9555	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	807406787	106056	0	0
T5	258111	5636	0	0
T6	504483	0	0	0
T7	6472	0	0	0
T8	646184	0	0	0
T9	12427	0	0	0
T10	103663	0	0	0
T11	7760	0	0	0
T12	52080	0	0	0
T40	0	17507	0	0
T42	0	5408	0	0
T43	0	6049	0	0
T44	0	1989	0	0
T45	512687	0	0	0
T91	2567	0	0	0
T92	0	12504	0	0
T93	0	10393	0	0
T94	0	3374	0	0
T95	0	961	0	0
T96	0	10994	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	807406787	92422	0	0
T5	258111	5044	0	0
T6	504483	0	0	0
T7	6472	0	0	0
T8	646184	0	0	0
T9	12427	0	0	0
T10	103663	0	0	0
T11	7760	0	0	0
T12	52080	0	0	0
T40	0	15751	0	0
T42	0	5007	0	0
T43	0	5370	0	0
T44	0	1781	0	0
T45	512687	0	0	0
T91	2567	0	0	0
T92	0	11021	0	0
T93	0	9514	0	0
T94	0	2505	0	0
T95	0	872	0	0
T96	0	9005	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	807406787	105001	0	0
T5	258111	5410	0	0
T6	504483	0	0	0
T7	6472	0	0	0
T8	646184	0	0	0
T9	12427	0	0	0
T10	103663	0	0	0
T11	7760	0	0	0
T12	52080	0	0	0
T40	0	17758	0	0
T42	0	5755	0	0
T43	0	5807	0	0
T44	0	2093	0	0
T45	512687	0	0	0
T91	2567	0	0	0
T92	0	12444	0	0
T93	0	11068	0	0
T94	0	3070	0	0
T95	0	1011	0	0
T96	0	10700	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	807406787	91858	0	0
T5	258111	5206	0	0
T6	504483	0	0	0
T7	6472	0	0	0
T8	646184	0	0	0
T9	12427	0	0	0
T10	103663	0	0	0
T11	7760	0	0	0
T12	52080	0	0	0
T40	0	15683	0	0
T42	0	4951	0	0
T43	0	5313	0	0
T44	0	1805	0	0
T45	512687	0	0	0
T91	2567	0	0	0
T92	0	10281	0	0
T93	0	9329	0	0
T94	0	2526	0	0
T95	0	800	0	0
T96	0	9368	0	0