Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	419982	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5125977	1		T1	239		T2	13		T3	218

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1362673	1		T1	56		T2	1		T3	39
values[0x0]	1961177	1		T1	152		T2	9		T3	139
values[0x1]	2222109	1		T1	153		T2	10		T3	126

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	185807	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5360152	1		T1	263		T2	18		T3	238

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21785	1		T1	12		T4	330		T5	324
valid_sources[0x01]	21019	1		T4	342		T5	377		T11	1257
valid_sources[0x02]	21438	1		T1	2		T4	339		T5	344
valid_sources[0x03]	22369	1		T1	1		T4	298		T5	341
valid_sources[0x04]	21394	1		T4	328		T5	348		T11	1117
valid_sources[0x05]	21159	1		T4	359		T5	323		T11	1261
valid_sources[0x06]	22754	1		T4	295		T5	320		T7	2
valid_sources[0x07]	22841	1		T4	332		T5	316		T7	1
valid_sources[0x08]	19508	1		T4	387		T5	297		T7	1
valid_sources[0x09]	22631	1		T4	300		T5	302		T11	1097
valid_sources[0x0a]	21092	1		T3	3		T4	325		T5	302
valid_sources[0x0b]	21228	1		T3	1		T4	288		T5	325
valid_sources[0x0c]	22200	1		T3	1		T4	345		T5	293
valid_sources[0x0d]	21356	1		T3	2		T4	308		T5	275
valid_sources[0x0e]	23326	1		T1	6		T3	2		T4	326
valid_sources[0x0f]	21571	1		T4	313		T5	334		T11	1153
valid_sources[0x10]	21335	1		T1	2		T4	339		T5	309
valid_sources[0x11]	21946	1		T1	2		T3	2		T4	369
valid_sources[0x12]	21693	1		T2	1		T4	317		T5	306
valid_sources[0x13]	22322	1		T1	2		T3	3		T4	268
valid_sources[0x14]	21927	1		T1	1		T4	294		T5	327
valid_sources[0x15]	21228	1		T3	1		T4	315		T5	301
valid_sources[0x16]	22024	1		T1	11		T3	1		T4	307
valid_sources[0x17]	21596	1		T4	251		T5	301		T8	1
valid_sources[0x18]	23634	1		T1	12		T4	338		T5	352
valid_sources[0x19]	21791	1		T4	271		T5	354		T7	1
valid_sources[0x1a]	21996	1		T3	9		T4	255		T5	316
valid_sources[0x1b]	21111	1		T1	7		T4	319		T5	335
valid_sources[0x1c]	21331	1		T4	314		T5	310		T11	1181
valid_sources[0x1d]	22361	1		T1	1		T3	1		T4	357
valid_sources[0x1e]	22854	1		T3	1		T4	354		T5	324
valid_sources[0x1f]	21646	1		T2	1		T3	7		T4	375
valid_sources[0x20]	21947	1		T3	2		T4	270		T5	318
valid_sources[0x21]	21894	1		T3	1		T4	356		T5	313
valid_sources[0x22]	22273	1		T4	385		T5	357		T11	1062
valid_sources[0x23]	20273	1		T3	4		T4	308		T5	298
valid_sources[0x24]	20587	1		T3	6		T4	299		T5	326
valid_sources[0x25]	20352	1		T4	361		T5	310		T7	2
valid_sources[0x26]	22205	1		T3	5		T4	280		T5	346
valid_sources[0x27]	21912	1		T1	9		T3	3		T4	306
valid_sources[0x28]	21200	1		T4	359		T5	305		T7	2
valid_sources[0x29]	20909	1		T1	1		T4	372		T5	327
valid_sources[0x2a]	22731	1		T3	1		T4	306		T5	309
valid_sources[0x2b]	21131	1		T1	10		T4	266		T5	324
valid_sources[0x2c]	21004	1		T1	2		T3	1		T4	277
valid_sources[0x2d]	21199	1		T4	327		T5	339		T7	1
valid_sources[0x2e]	21763	1		T3	8		T4	312		T5	350
valid_sources[0x2f]	21050	1		T1	9		T4	296		T5	335
valid_sources[0x30]	22353	1		T4	345		T5	301		T7	2
valid_sources[0x31]	21506	1		T1	4		T4	345		T5	285
valid_sources[0x32]	21963	1		T1	4		T3	2		T4	365
valid_sources[0x33]	21963	1		T4	299		T5	300		T11	1231
valid_sources[0x34]	22103	1		T4	306		T5	275		T11	1161
valid_sources[0x35]	21521	1		T3	4		T4	317		T5	296
valid_sources[0x36]	21748	1		T3	3		T4	341		T5	355
valid_sources[0x37]	21059	1		T3	2		T4	238		T5	307
valid_sources[0x38]	21191	1		T3	1		T4	315		T5	298
valid_sources[0x39]	22083	1		T4	348		T5	323		T7	3
valid_sources[0x3a]	20531	1		T3	2		T4	311		T5	342
valid_sources[0x3b]	21547	1		T1	2		T3	1		T4	328
valid_sources[0x3c]	22937	1		T3	2		T4	285		T5	349
valid_sources[0x3d]	20040	1		T3	1		T4	324		T5	322
valid_sources[0x3e]	21942	1		T1	1		T3	1		T4	341
valid_sources[0x3f]	21410	1		T1	1		T3	4		T4	309
valid_sources[0x40]	22660	1		T1	2		T3	1		T4	331
valid_sources[0x41]	21407	1		T4	292		T5	255		T11	1111
valid_sources[0x42]	20400	1		T3	5		T4	332		T5	280
valid_sources[0x43]	21147	1		T3	2		T4	327		T5	312
valid_sources[0x44]	21697	1		T4	342		T5	304		T11	1199
valid_sources[0x45]	21417	1		T4	388		T5	335		T8	1
valid_sources[0x46]	22893	1		T1	8		T3	1		T4	311
valid_sources[0x47]	22171	1		T1	1		T3	3		T4	365
valid_sources[0x48]	20630	1		T3	2		T4	315		T5	288
valid_sources[0x49]	21328	1		T4	350		T5	351		T7	1
valid_sources[0x4a]	21539	1		T1	2		T4	371		T5	336
valid_sources[0x4b]	22657	1		T3	3		T4	267		T5	306
valid_sources[0x4c]	21512	1		T4	284		T5	375		T7	1
valid_sources[0x4d]	20706	1		T1	2		T4	418		T5	336
valid_sources[0x4e]	22028	1		T4	335		T5	365		T11	1189
valid_sources[0x4f]	21176	1		T3	2		T4	304		T5	283
valid_sources[0x50]	20444	1		T4	298		T5	324		T11	1244
valid_sources[0x51]	21270	1		T1	8		T3	4		T4	304
valid_sources[0x52]	22398	1		T4	325		T5	348		T6	1
valid_sources[0x53]	21735	1		T3	3		T4	324		T5	295
valid_sources[0x54]	22975	1		T3	9		T4	324		T5	302
valid_sources[0x55]	21166	1		T1	5		T4	320		T5	346
valid_sources[0x56]	21119	1		T1	1		T4	317		T5	319
valid_sources[0x57]	22479	1		T3	6		T4	333		T5	323
valid_sources[0x58]	21886	1		T3	6		T4	308		T5	328
valid_sources[0x59]	20900	1		T4	318		T5	294		T7	2
valid_sources[0x5a]	21183	1		T1	3		T4	229		T5	345
valid_sources[0x5b]	20849	1		T1	4		T3	2		T4	394
valid_sources[0x5c]	21474	1		T3	2		T4	300		T5	325
valid_sources[0x5d]	21132	1		T1	2		T4	294		T5	341
valid_sources[0x5e]	21777	1		T1	3		T4	335		T5	329
valid_sources[0x5f]	22495	1		T1	10		T3	1		T4	332
valid_sources[0x60]	22341	1		T4	373		T5	351		T11	1134
valid_sources[0x61]	20891	1		T4	290		T5	351		T7	2
valid_sources[0x62]	21588	1		T4	361		T5	315		T7	1
valid_sources[0x63]	20937	1		T4	275		T5	321		T7	2
valid_sources[0x64]	21273	1		T4	291		T5	372		T7	3
valid_sources[0x65]	21875	1		T1	2		T4	273		T5	324
valid_sources[0x66]	22330	1		T4	317		T5	316		T11	1130
valid_sources[0x67]	22789	1		T4	339		T5	352		T11	1257
valid_sources[0x68]	22041	1		T3	5		T4	341		T5	290
valid_sources[0x69]	22110	1		T1	2		T4	308		T5	305
valid_sources[0x6a]	22512	1		T3	2		T4	331		T5	318
valid_sources[0x6b]	20723	1		T1	3		T4	316		T5	308
valid_sources[0x6c]	23048	1		T1	1		T3	4		T4	278
valid_sources[0x6d]	21068	1		T3	2		T4	284		T5	323
valid_sources[0x6e]	21735	1		T1	1		T3	1		T4	320
valid_sources[0x6f]	22017	1		T4	365		T5	337		T7	4
valid_sources[0x70]	21978	1		T4	342		T5	289		T7	1
valid_sources[0x71]	22002	1		T4	344		T5	342		T7	2
valid_sources[0x72]	22417	1		T1	5		T4	284		T5	303
valid_sources[0x73]	21849	1		T3	3		T4	345		T5	359
valid_sources[0x74]	20743	1		T2	1		T4	231		T5	292
valid_sources[0x75]	21266	1		T4	296		T5	315		T11	1181
valid_sources[0x76]	21185	1		T4	282		T5	324		T7	1
valid_sources[0x77]	22251	1		T4	328		T5	335		T11	1115
valid_sources[0x78]	21927	1		T3	1		T4	309		T5	347
valid_sources[0x79]	22739	1		T3	1		T4	316		T5	368
valid_sources[0x7a]	20548	1		T4	325		T5	342		T11	1145
valid_sources[0x7b]	22776	1		T1	2		T4	298		T5	294
valid_sources[0x7c]	21509	1		T3	1		T4	318		T5	322
valid_sources[0x7d]	22822	1		T4	323		T5	330		T7	2
valid_sources[0x7e]	20959	1		T4	304		T5	286		T11	1131
valid_sources[0x7f]	19624	1		T1	1		T3	3		T4	331
valid_sources[0x80]	21706	1		T4	248		T5	301		T11	1193

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1277919

1

T1

25

T2

1

T3

21

values[0x0]

all_enables

biggest_size

1926872

1

T1

111

T2

7

T3

111

values[0x1]

all_enables

biggest_size

1921186

1

T1

103

T2

5

T3

86