Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	707236148	6110435	0	0
wdog_bark_thold_rd_A	707236148	101759	0	0
wdog_bite_thold_rd_A	707236148	88763	0	0
wdog_ctrl_rd_A	707236148	89242	0	0
wdog_regwen_rd_A	707236148	101884	0	0
wkup_ctrl_rd_A	707236148	89907	0	0
wkup_thold_hi_rd_A	707236148	100703	0	0
wkup_thold_lo_rd_A	707236148	89262	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707236148	6110435	0	0
T4	396180	85912	0	0
T5	525821	91806	0	0
T6	12524	0	0	0
T7	908601	0	0	0
T8	38319	0	0	0
T9	53444	0	0	0
T10	546898	0	0	0
T11	893111	325096	0	0
T12	466438	0	0	0
T13	13835	0	0	0
T26	0	92042	0	0
T35	0	177124	0	0
T36	0	227608	0	0
T37	0	109364	0	0
T38	0	205447	0	0
T39	0	63161	0	0
T40	0	107432	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707236148	101759	0	0
T4	396180	8427	0	0
T5	525821	0	0	0
T6	12524	0	0	0
T7	908601	0	0	0
T8	38319	0	0	0
T9	53444	0	0	0
T10	546898	0	0	0
T11	893111	0	0	0
T12	466438	0	0	0
T13	13835	0	0	0
T26	0	9700	0	0
T71	0	2976	0	0
T77	0	7761	0	0
T78	0	3856	0	0
T79	0	34120	0	0
T80	0	4591	0	0
T81	0	16757	0	0
T82	0	8034	0	0
T83	0	4309	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707236148	88763	0	0
T4	396180	7434	0	0
T5	525821	0	0	0
T6	12524	0	0	0
T7	908601	0	0	0
T8	38319	0	0	0
T9	53444	0	0	0
T10	546898	0	0	0
T11	893111	0	0	0
T12	466438	0	0	0
T13	13835	0	0	0
T26	0	8292	0	0
T71	0	2654	0	0
T77	0	6503	0	0
T78	0	3673	0	0
T79	0	29926	0	0
T80	0	3427	0	0
T81	0	15483	0	0
T82	0	6789	0	0
T83	0	3345	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707236148	89242	0	0
T4	396180	7465	0	0
T5	525821	0	0	0
T6	12524	0	0	0
T7	908601	0	0	0
T8	38319	0	0	0
T9	53444	0	0	0
T10	546898	0	0	0
T11	893111	0	0	0
T12	466438	0	0	0
T13	13835	0	0	0
T26	0	8227	0	0
T71	0	2603	0	0
T77	0	6379	0	0
T78	0	3461	0	0
T79	0	29918	0	0
T80	0	3675	0	0
T81	0	15713	0	0
T82	0	7125	0	0
T83	0	3414	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707236148	101884	0	0
T4	396180	8222	0	0
T5	525821	0	0	0
T6	12524	0	0	0
T7	908601	0	0	0
T8	38319	0	0	0
T9	53444	0	0	0
T10	546898	0	0	0
T11	893111	0	0	0
T12	466438	0	0	0
T13	13835	0	0	0
T26	0	9052	0	0
T71	0	3131	0	0
T77	0	7620	0	0
T78	0	4293	0	0
T79	0	34089	0	0
T80	0	4046	0	0
T81	0	17912	0	0
T82	0	8314	0	0
T83	0	4054	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707236148	89907	0	0
T4	396180	7239	0	0
T5	525821	0	0	0
T6	12524	0	0	0
T7	908601	0	0	0
T8	38319	0	0	0
T9	53444	0	0	0
T10	546898	0	0	0
T11	893111	0	0	0
T12	466438	0	0	0
T13	13835	0	0	0
T26	0	7946	0	0
T71	0	2505	0	0
T77	0	6354	0	0
T78	0	3595	0	0
T79	0	30848	0	0
T80	0	3961	0	0
T81	0	15617	0	0
T82	0	6963	0	0
T83	0	3583	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707236148	100703	0	0
T4	396180	8317	0	0
T5	525821	0	0	0
T6	12524	0	0	0
T7	908601	0	0	0
T8	38319	0	0	0
T9	53444	0	0	0
T10	546898	0	0	0
T11	893111	0	0	0
T12	466438	0	0	0
T13	13835	0	0	0
T26	0	9532	0	0
T71	0	2706	0	0
T77	0	7863	0	0
T78	0	4110	0	0
T79	0	33705	0	0
T80	0	4311	0	0
T81	0	17264	0	0
T82	0	7514	0	0
T83	0	4022	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707236148	89262	0	0
T4	396180	7337	0	0
T5	525821	0	0	0
T6	12524	0	0	0
T7	908601	0	0	0
T8	38319	0	0	0
T9	53444	0	0	0
T10	546898	0	0	0
T11	893111	0	0	0
T12	466438	0	0	0
T13	13835	0	0	0
T26	0	8390	0	0
T71	0	2378	0	0
T77	0	7271	0	0
T78	0	3557	0	0
T79	0	29497	0	0
T80	0	3676	0	0
T81	0	15651	0	0
T82	0	6812	0	0
T83	0	3471	0	0