Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	332220	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4085894	1		T1	12		T2	14		T3	229

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1085641	1		T1	1		T2	1		T3	40
values[0x0]	1561673	1		T1	5		T2	9		T3	137
values[0x1]	1770800	1		T1	13		T2	10		T3	147

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	147656	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4270458	1		T1	13		T2	14		T3	253

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17854	1		T8	158		T10	1		T11	1
valid_sources[0x01]	17744	1		T1	3		T3	2		T8	193
valid_sources[0x02]	17346	1		T3	2		T8	146		T10	1
valid_sources[0x03]	16725	1		T3	2		T8	263		T11	1
valid_sources[0x04]	16600	1		T8	188		T12	527		T13	3
valid_sources[0x05]	17142	1		T3	1		T8	267		T11	1
valid_sources[0x06]	16117	1		T8	170		T10	1		T11	7
valid_sources[0x07]	17159	1		T3	1		T8	201		T10	2
valid_sources[0x08]	18505	1		T1	2		T8	233		T10	13
valid_sources[0x09]	17589	1		T3	1		T6	8		T8	175
valid_sources[0x0a]	17224	1		T8	165		T11	4		T12	594
valid_sources[0x0b]	16369	1		T4	1		T8	156		T12	638
valid_sources[0x0c]	17280	1		T3	1		T8	152		T12	632
valid_sources[0x0d]	18053	1		T8	176		T10	2		T11	1
valid_sources[0x0e]	18680	1		T8	181		T12	553		T13	1
valid_sources[0x0f]	16868	1		T8	194		T11	3		T12	588
valid_sources[0x10]	16992	1		T3	2		T8	225		T12	570
valid_sources[0x11]	16385	1		T8	180		T11	2		T12	544
valid_sources[0x12]	17604	1		T3	1		T8	164		T12	515
valid_sources[0x13]	17040	1		T5	1		T7	1		T8	220
valid_sources[0x14]	16361	1		T3	1		T8	195		T12	508
valid_sources[0x15]	18012	1		T3	4		T4	1		T8	158
valid_sources[0x16]	17432	1		T3	1		T8	186		T12	538
valid_sources[0x17]	16479	1		T3	2		T7	7		T8	152
valid_sources[0x18]	16963	1		T2	3		T4	1		T8	198
valid_sources[0x19]	16709	1		T3	1		T8	203		T10	4
valid_sources[0x1a]	17750	1		T3	2		T8	198		T10	2
valid_sources[0x1b]	17699	1		T8	186		T12	546		T13	1
valid_sources[0x1c]	17595	1		T3	3		T8	162		T10	2
valid_sources[0x1d]	17837	1		T1	1		T3	2		T8	166
valid_sources[0x1e]	16606	1		T3	1		T8	173		T11	4
valid_sources[0x1f]	17696	1		T3	1		T8	153		T10	4
valid_sources[0x20]	17165	1		T3	1		T8	286		T12	487
valid_sources[0x21]	17921	1		T3	2		T8	150		T10	5
valid_sources[0x22]	16318	1		T1	1		T3	1		T8	124
valid_sources[0x23]	15732	1		T3	3		T8	186		T10	5
valid_sources[0x24]	16052	1		T3	4		T8	175		T10	1
valid_sources[0x25]	16400	1		T1	1		T3	1		T8	137
valid_sources[0x26]	16011	1		T3	1		T8	182		T10	3
valid_sources[0x27]	18113	1		T3	2		T8	191		T12	588
valid_sources[0x28]	17765	1		T3	3		T8	183		T10	1
valid_sources[0x29]	17111	1		T1	1		T3	2		T8	246
valid_sources[0x2a]	16806	1		T3	3		T8	192		T11	1
valid_sources[0x2b]	18775	1		T8	190		T10	2		T11	4
valid_sources[0x2c]	16852	1		T8	164		T11	4		T12	452
valid_sources[0x2d]	17327	1		T3	1		T4	2		T8	138
valid_sources[0x2e]	17891	1		T8	196		T12	489		T14	346
valid_sources[0x2f]	18169	1		T3	4		T8	217		T12	533
valid_sources[0x30]	18142	1		T8	269		T10	1		T11	3
valid_sources[0x31]	18741	1		T3	2		T8	230		T11	4
valid_sources[0x32]	17630	1		T7	10		T8	196		T10	1
valid_sources[0x33]	18176	1		T3	2		T8	230		T11	1
valid_sources[0x34]	18100	1		T3	2		T8	185		T10	4
valid_sources[0x35]	18013	1		T3	2		T8	164		T11	9
valid_sources[0x36]	17149	1		T3	1		T4	1		T8	200
valid_sources[0x37]	18683	1		T8	194		T11	1		T12	493
valid_sources[0x38]	16889	1		T8	148		T11	2		T12	516
valid_sources[0x39]	16935	1		T3	1		T8	156		T12	494
valid_sources[0x3a]	17168	1		T3	2		T8	186		T10	1
valid_sources[0x3b]	17217	1		T8	144		T10	4		T12	572
valid_sources[0x3c]	17510	1		T8	212		T10	7		T12	485
valid_sources[0x3d]	17392	1		T3	1		T8	204		T12	493
valid_sources[0x3e]	18264	1		T3	1		T8	231		T10	1
valid_sources[0x3f]	17383	1		T3	1		T8	187		T12	459
valid_sources[0x40]	17378	1		T3	4		T8	230		T11	6
valid_sources[0x41]	18218	1		T8	234		T10	3		T11	1
valid_sources[0x42]	17928	1		T8	177		T12	543		T13	3
valid_sources[0x43]	16502	1		T8	158		T10	2		T11	2
valid_sources[0x44]	16334	1		T1	1		T3	2		T8	151
valid_sources[0x45]	18386	1		T8	216		T10	4		T11	2
valid_sources[0x46]	17280	1		T8	205		T12	520		T13	9
valid_sources[0x47]	17146	1		T3	1		T8	165		T12	463
valid_sources[0x48]	16899	1		T3	2		T8	205		T12	488
valid_sources[0x49]	18055	1		T1	2		T8	198		T12	511
valid_sources[0x4a]	16807	1		T3	2		T8	238		T10	1
valid_sources[0x4b]	18592	1		T8	235		T12	511		T21	1
valid_sources[0x4c]	16890	1		T3	2		T8	207		T11	2
valid_sources[0x4d]	16117	1		T8	142		T11	1		T12	537
valid_sources[0x4e]	17180	1		T8	204		T10	1		T11	3
valid_sources[0x4f]	16324	1		T8	166		T12	405		T21	3
valid_sources[0x50]	16856	1		T8	185		T12	535		T13	3
valid_sources[0x51]	17021	1		T3	3		T8	154		T12	519
valid_sources[0x52]	15794	1		T3	2		T8	141		T12	456
valid_sources[0x53]	16299	1		T8	187		T12	550		T13	7
valid_sources[0x54]	16379	1		T3	1		T4	1		T8	167
valid_sources[0x55]	17190	1		T8	198		T11	1		T12	580
valid_sources[0x56]	16863	1		T3	1		T8	237		T11	1
valid_sources[0x57]	16444	1		T3	2		T8	175		T27	1
valid_sources[0x58]	18583	1		T8	194		T10	10		T11	1
valid_sources[0x59]	17668	1		T2	1		T8	195		T10	5
valid_sources[0x5a]	16029	1		T8	229		T10	3		T12	481
valid_sources[0x5b]	16953	1		T3	4		T8	139		T10	2
valid_sources[0x5c]	16256	1		T3	3		T8	203		T11	1
valid_sources[0x5d]	18064	1		T3	7		T8	212		T11	3
valid_sources[0x5e]	18287	1		T3	4		T8	193		T10	1
valid_sources[0x5f]	17586	1		T3	2		T8	205		T11	3
valid_sources[0x60]	17420	1		T1	1		T3	3		T8	190
valid_sources[0x61]	18162	1		T8	254		T12	462		T14	304
valid_sources[0x62]	15854	1		T3	1		T8	232		T10	6
valid_sources[0x63]	17031	1		T1	1		T3	1		T8	198
valid_sources[0x64]	16494	1		T8	184		T12	528		T21	1
valid_sources[0x65]	16792	1		T3	2		T8	213		T11	4
valid_sources[0x66]	17892	1		T4	1		T8	177		T10	3
valid_sources[0x67]	16315	1		T3	4		T8	228		T11	5
valid_sources[0x68]	17344	1		T2	1		T3	1		T8	232
valid_sources[0x69]	16914	1		T3	4		T8	219		T11	4
valid_sources[0x6a]	16217	1		T8	176		T27	1		T12	521
valid_sources[0x6b]	16830	1		T3	1		T8	240		T12	553
valid_sources[0x6c]	18067	1		T8	178		T11	5		T12	521
valid_sources[0x6d]	17263	1		T3	2		T8	155		T12	573
valid_sources[0x6e]	17486	1		T3	2		T4	1		T8	196
valid_sources[0x6f]	17649	1		T3	1		T8	174		T11	1
valid_sources[0x70]	17976	1		T3	1		T8	150		T12	535
valid_sources[0x71]	17618	1		T8	153		T10	6		T11	3
valid_sources[0x72]	16689	1		T8	191		T11	1		T27	2
valid_sources[0x73]	16423	1		T3	1		T8	235		T12	481
valid_sources[0x74]	17598	1		T3	3		T8	183		T12	569
valid_sources[0x75]	17739	1		T8	188		T10	1		T12	511
valid_sources[0x76]	18065	1		T3	1		T8	210		T12	505
valid_sources[0x77]	17315	1		T8	160		T11	2		T12	518
valid_sources[0x78]	16333	1		T3	1		T8	207		T10	1
valid_sources[0x79]	17188	1		T8	214		T10	2		T12	570
valid_sources[0x7a]	17243	1		T3	2		T8	254		T11	1
valid_sources[0x7b]	16504	1		T8	166		T11	2		T12	559
valid_sources[0x7c]	15831	1		T8	165		T11	1		T12	558
valid_sources[0x7d]	17792	1		T8	223		T10	4		T11	4
valid_sources[0x7e]	17687	1		T3	4		T8	177		T10	5
valid_sources[0x7f]	17244	1		T8	224		T10	1		T12	583
valid_sources[0x80]	18402	1		T3	2		T8	261		T10	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1018438

1

T2

1

T3

16

T6

1

values[0x0]

all_enables

biggest_size

1534130

1

T1

5

T2

5

T3

109

values[0x1]

all_enables

biggest_size

1533326

1

T1

7

T2

8

T3

104