Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	860209011	4799818	0	0
wdog_bark_thold_rd_A	860209011	109894	0	0
wdog_bite_thold_rd_A	860209011	93850	0	0
wdog_ctrl_rd_A	860209011	94844	0	0
wdog_regwen_rd_A	860209011	108746	0	0
wkup_ctrl_rd_A	860209011	93472	0	0
wkup_thold_hi_rd_A	860209011	108266	0	0
wkup_thold_lo_rd_A	860209011	95108	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	860209011	4799818	0	0
T8	226231	56284	0	0
T9	47419	0	0	0
T10	740626	0	0	0
T11	117480	0	0	0
T12	463079	153902	0	0
T13	943528	0	0	0
T14	0	102022	0	0
T15	222740	0	0	0
T20	10205	0	0	0
T21	106369	0	0	0
T26	0	159572	0	0
T27	16708	0	0	0
T35	0	297944	0	0
T36	0	35149	0	0
T37	0	134448	0	0
T38	0	31407	0	0
T39	0	155965	0	0
T40	0	46401	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	860209011	109894	0	0
T36	153349	3317	0	0
T37	370890	0	0	0
T38	135576	3050	0	0
T43	136344	0	0	0
T44	50391	0	0	0
T70	0	425	0	0
T71	0	28765	0	0
T72	0	4648	0	0
T73	0	6065	0	0
T74	0	1186	0	0
T75	0	9655	0	0
T76	0	8596	0	0
T77	0	9515	0	0
T78	10295	0	0	0
T79	101059	0	0	0
T80	26864	0	0	0
T81	403944	0	0	0
T82	137586	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	860209011	93850	0	0
T36	153349	2899	0	0
T37	370890	0	0	0
T38	135576	2383	0	0
T43	136344	0	0	0
T44	50391	0	0	0
T70	0	365	0	0
T71	0	23845	0	0
T72	0	3903	0	0
T73	0	5094	0	0
T74	0	1111	0	0
T75	0	8725	0	0
T76	0	7320	0	0
T77	0	8333	0	0
T78	10295	0	0	0
T79	101059	0	0	0
T80	26864	0	0	0
T81	403944	0	0	0
T82	137586	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	860209011	94844	0	0
T36	153349	2850	0	0
T37	370890	0	0	0
T38	135576	2754	0	0
T43	136344	0	0	0
T44	50391	0	0	0
T70	0	314	0	0
T71	0	24301	0	0
T72	0	3762	0	0
T73	0	4717	0	0
T74	0	1183	0	0
T75	0	8964	0	0
T76	0	7147	0	0
T77	0	8355	0	0
T78	10295	0	0	0
T79	101059	0	0	0
T80	26864	0	0	0
T81	403944	0	0	0
T82	137586	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	860209011	108746	0	0
T36	153349	3441	0	0
T37	370890	0	0	0
T38	135576	3298	0	0
T43	136344	0	0	0
T44	50391	0	0	0
T70	0	483	0	0
T71	0	27796	0	0
T72	0	4510	0	0
T73	0	5864	0	0
T74	0	1392	0	0
T75	0	9841	0	0
T76	0	8439	0	0
T77	0	9665	0	0
T78	10295	0	0	0
T79	101059	0	0	0
T80	26864	0	0	0
T81	403944	0	0	0
T82	137586	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	860209011	93472	0	0
T36	153349	2944	0	0
T37	370890	0	0	0
T38	135576	2612	0	0
T43	136344	0	0	0
T44	50391	0	0	0
T70	0	302	0	0
T71	0	23383	0	0
T72	0	3796	0	0
T73	0	5038	0	0
T74	0	1163	0	0
T75	0	8790	0	0
T76	0	7509	0	0
T77	0	8516	0	0
T78	10295	0	0	0
T79	101059	0	0	0
T80	26864	0	0	0
T81	403944	0	0	0
T82	137586	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	860209011	108266	0	0
T36	153349	3343	0	0
T37	370890	0	0	0
T38	135576	2828	0	0
T43	136344	0	0	0
T44	50391	0	0	0
T70	0	471	0	0
T71	0	28198	0	0
T72	0	4454	0	0
T73	0	5614	0	0
T74	0	1457	0	0
T75	0	10244	0	0
T76	0	8042	0	0
T77	0	9219	0	0
T78	10295	0	0	0
T79	101059	0	0	0
T80	26864	0	0	0
T81	403944	0	0	0
T82	137586	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	860209011	95108	0	0
T36	153349	2848	0	0
T37	370890	0	0	0
T38	135576	2682	0	0
T43	136344	0	0	0
T44	50391	0	0	0
T70	0	410	0	0
T71	0	24331	0	0
T72	0	4021	0	0
T73	0	4858	0	0
T74	0	1380	0	0
T75	0	8457	0	0
T76	0	7627	0	0
T77	0	8457	0	0
T78	10295	0	0	0
T79	101059	0	0	0
T80	26864	0	0	0
T81	403944	0	0	0
T82	137586	0	0	0