Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	338737	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4121271	1		T1	11		T2	210		T3	106542

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1096715	1		T1	1		T2	37		T3	28261
values[0x0]	1575544	1		T1	8		T2	141		T3	40464
values[0x1]	1787749	1		T1	9		T2	135		T3	46543

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151572	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4308436	1		T1	11		T2	233		T3	111633

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16736	1		T3	254		T6	1100		T12	2
valid_sources[0x01]	16701	1		T2	1		T3	367		T6	1121
valid_sources[0x02]	17569	1		T1	1		T2	1		T3	25
valid_sources[0x03]	17073	1		T2	4		T3	304		T6	883
valid_sources[0x04]	17933	1		T2	1		T3	197		T6	1009
valid_sources[0x05]	16760	1		T2	1		T3	147		T6	924
valid_sources[0x06]	17380	1		T2	2		T3	268		T6	1109
valid_sources[0x07]	17550	1		T3	373		T6	977		T9	4
valid_sources[0x08]	17483	1		T3	340		T6	1028		T16	922
valid_sources[0x09]	17633	1		T3	622		T6	1098		T12	2
valid_sources[0x0a]	18826	1		T3	1140		T6	1086		T12	1
valid_sources[0x0b]	16005	1		T2	1		T3	183		T6	843
valid_sources[0x0c]	18025	1		T2	1		T3	314		T6	930
valid_sources[0x0d]	17485	1		T2	3		T3	902		T5	1
valid_sources[0x0e]	17310	1		T2	2		T3	276		T6	1199
valid_sources[0x0f]	17217	1		T3	347		T6	1159		T16	802
valid_sources[0x10]	18170	1		T3	640		T6	895		T9	5
valid_sources[0x11]	19092	1		T3	756		T6	1236		T7	1
valid_sources[0x12]	17841	1		T3	302		T6	1150		T16	356
valid_sources[0x13]	16582	1		T2	3		T3	3		T6	1039
valid_sources[0x14]	19555	1		T2	2		T3	674		T6	1263
valid_sources[0x15]	16858	1		T3	339		T6	997		T12	2
valid_sources[0x16]	16590	1		T2	1		T3	363		T6	1169
valid_sources[0x17]	17503	1		T3	462		T5	1		T6	1129
valid_sources[0x18]	16959	1		T3	193		T6	1008		T9	1
valid_sources[0x19]	18564	1		T2	1		T3	647		T6	1050
valid_sources[0x1a]	17347	1		T1	2		T3	801		T6	1225
valid_sources[0x1b]	18403	1		T2	3		T3	833		T6	794
valid_sources[0x1c]	17267	1		T3	574		T6	1026		T15	2
valid_sources[0x1d]	18090	1		T2	3		T3	1090		T6	1258
valid_sources[0x1e]	17712	1		T3	308		T6	1005		T12	2
valid_sources[0x1f]	18473	1		T3	1073		T6	1074		T12	2
valid_sources[0x20]	16786	1		T2	1		T3	71		T6	1023
valid_sources[0x21]	18204	1		T3	771		T6	946		T9	2
valid_sources[0x22]	17748	1		T3	463		T6	982		T10	1
valid_sources[0x23]	17459	1		T3	506		T6	917		T12	1
valid_sources[0x24]	16482	1		T3	3		T6	831		T12	1
valid_sources[0x25]	17034	1		T2	1		T3	459		T6	1076
valid_sources[0x26]	17308	1		T1	1		T2	1		T3	474
valid_sources[0x27]	18455	1		T3	860		T6	990		T12	3
valid_sources[0x28]	16812	1		T2	1		T3	156		T6	999
valid_sources[0x29]	16946	1		T2	2		T3	809		T6	1067
valid_sources[0x2a]	18026	1		T3	988		T6	935		T12	2
valid_sources[0x2b]	16494	1		T2	3		T3	184		T6	1096
valid_sources[0x2c]	16543	1		T2	2		T3	80		T6	996
valid_sources[0x2d]	16789	1		T2	1		T3	92		T6	1117
valid_sources[0x2e]	17500	1		T3	209		T6	1237		T15	3
valid_sources[0x2f]	18160	1		T3	995		T6	1003		T9	5
valid_sources[0x30]	16278	1		T2	1		T3	256		T5	3
valid_sources[0x31]	17319	1		T2	1		T3	601		T6	897
valid_sources[0x32]	17577	1		T3	337		T6	1011		T12	2
valid_sources[0x33]	16116	1		T3	259		T6	1016		T15	1
valid_sources[0x34]	18055	1		T2	3		T3	516		T6	883
valid_sources[0x35]	16573	1		T2	1		T3	28		T6	1008
valid_sources[0x36]	17911	1		T3	641		T6	885		T9	4
valid_sources[0x37]	17848	1		T3	298		T5	1		T6	1098
valid_sources[0x38]	17370	1		T3	534		T6	1044		T9	10
valid_sources[0x39]	16817	1		T3	362		T6	1235		T11	1
valid_sources[0x3a]	16820	1		T3	703		T6	972		T16	141
valid_sources[0x3b]	17592	1		T3	402		T6	1075		T12	1
valid_sources[0x3c]	16725	1		T2	1		T3	778		T6	983
valid_sources[0x3d]	17706	1		T3	227		T6	936		T12	1
valid_sources[0x3e]	17875	1		T2	6		T3	57		T6	1009
valid_sources[0x3f]	16237	1		T2	2		T3	464		T6	1238
valid_sources[0x40]	17627	1		T3	309		T6	951		T9	2
valid_sources[0x41]	16707	1		T2	4		T3	391		T6	1061
valid_sources[0x42]	17436	1		T2	3		T3	440		T5	2
valid_sources[0x43]	17716	1		T2	1		T3	608		T6	886
valid_sources[0x44]	17815	1		T2	2		T3	604		T6	872
valid_sources[0x45]	18141	1		T2	1		T3	842		T6	958
valid_sources[0x46]	17593	1		T3	261		T6	778		T15	3
valid_sources[0x47]	16628	1		T3	139		T6	1100		T12	1
valid_sources[0x48]	17407	1		T2	5		T3	16		T6	1039
valid_sources[0x49]	17263	1		T2	5		T3	554		T6	1043
valid_sources[0x4a]	17099	1		T3	445		T6	908		T9	1
valid_sources[0x4b]	17462	1		T2	2		T3	329		T6	1079
valid_sources[0x4c]	17608	1		T2	1		T3	142		T6	1116
valid_sources[0x4d]	18324	1		T2	2		T3	395		T6	969
valid_sources[0x4e]	16558	1		T3	285		T6	1026		T9	5
valid_sources[0x4f]	18491	1		T2	3		T3	855		T6	1013
valid_sources[0x50]	17707	1		T1	1		T2	2		T3	155
valid_sources[0x51]	17429	1		T3	513		T6	1045		T12	1
valid_sources[0x52]	17682	1		T3	1049		T6	996		T10	1
valid_sources[0x53]	17086	1		T2	3		T3	286		T6	856
valid_sources[0x54]	17260	1		T2	8		T3	484		T6	843
valid_sources[0x55]	17587	1		T2	2		T3	282		T6	1047
valid_sources[0x56]	17499	1		T2	1		T3	578		T6	1026
valid_sources[0x57]	18789	1		T3	1201		T6	1063		T12	4
valid_sources[0x58]	17220	1		T3	606		T6	1055		T9	6
valid_sources[0x59]	18299	1		T2	1		T3	378		T6	1169
valid_sources[0x5a]	17210	1		T2	2		T3	339		T6	1044
valid_sources[0x5b]	17109	1		T3	371		T6	990		T12	1
valid_sources[0x5c]	17298	1		T2	3		T3	732		T6	1039
valid_sources[0x5d]	17900	1		T3	1054		T6	1187		T12	1
valid_sources[0x5e]	17627	1		T3	613		T6	997		T12	4
valid_sources[0x5f]	16348	1		T2	1		T3	348		T6	1039
valid_sources[0x60]	17057	1		T2	2		T3	122		T6	1010
valid_sources[0x61]	17498	1		T3	200		T6	982		T15	1
valid_sources[0x62]	16999	1		T2	2		T3	692		T6	993
valid_sources[0x63]	17354	1		T3	342		T6	1028		T9	4
valid_sources[0x64]	18727	1		T2	2		T3	762		T6	1127
valid_sources[0x65]	17702	1		T3	411		T6	884		T9	1
valid_sources[0x66]	17710	1		T2	1		T3	418		T6	842
valid_sources[0x67]	16225	1		T2	4		T3	445		T6	996
valid_sources[0x68]	16775	1		T2	3		T3	298		T6	899
valid_sources[0x69]	17374	1		T2	3		T3	536		T6	801
valid_sources[0x6a]	17307	1		T3	812		T6	942		T12	2
valid_sources[0x6b]	18457	1		T2	1		T3	1032		T6	1005
valid_sources[0x6c]	17391	1		T2	1		T3	685		T6	945
valid_sources[0x6d]	17452	1		T1	1		T2	5		T3	764
valid_sources[0x6e]	16420	1		T2	1		T3	300		T6	957
valid_sources[0x6f]	18341	1		T2	4		T3	813		T6	1037
valid_sources[0x70]	16687	1		T2	3		T3	487		T6	1041
valid_sources[0x71]	17898	1		T3	134		T6	1130		T7	1
valid_sources[0x72]	17851	1		T3	533		T6	973		T7	1
valid_sources[0x73]	17132	1		T2	3		T3	285		T6	1008
valid_sources[0x74]	15907	1		T3	351		T6	947		T16	481
valid_sources[0x75]	17155	1		T2	5		T3	201		T6	1143
valid_sources[0x76]	17566	1		T2	1		T3	74		T6	931
valid_sources[0x77]	17774	1		T2	1		T3	651		T6	981
valid_sources[0x78]	17704	1		T3	350		T6	943		T9	2
valid_sources[0x79]	17421	1		T3	243		T6	992		T12	2
valid_sources[0x7a]	17280	1		T2	2		T3	1338		T6	983
valid_sources[0x7b]	16856	1		T3	693		T6	1013		T12	4
valid_sources[0x7c]	17412	1		T2	2		T3	476		T6	983
valid_sources[0x7d]	15574	1		T2	2		T3	294		T5	1
valid_sources[0x7e]	17723	1		T2	5		T3	426		T6	1023
valid_sources[0x7f]	17172	1		T3	526		T6	1100		T12	1
valid_sources[0x80]	16387	1		T2	3		T3	294		T6	978

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1027876

1

T2

16

T3

26608

T6

60151

values[0x0]

all_enables

biggest_size

1546905

1

T1

6

T2

103

T3

39871

values[0x1]

all_enables

biggest_size

1546490

1

T1

5

T2

91

T3

40063