Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	691875694	4918306	0	0
wdog_bark_thold_rd_A	691875694	117502	0	0
wdog_bite_thold_rd_A	691875694	102748	0	0
wdog_ctrl_rd_A	691875694	103131	0	0
wdog_regwen_rd_A	691875694	117134	0	0
wkup_ctrl_rd_A	691875694	102471	0	0
wkup_thold_hi_rd_A	691875694	118704	0	0
wkup_thold_lo_rd_A	691875694	102045	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	691875694	4918306	0	0
T3	486733	132534	0	0
T5	4438	0	0	0
T6	119507	283789	0	0
T7	20554	0	0	0
T8	509669	0	0	0
T9	305214	0	0	0
T10	7269	0	0	0
T11	44760	0	0	0
T12	211021	0	0	0
T13	209845	0	0	0
T16	0	160811	0	0
T24	0	190289	0	0
T25	0	104185	0	0
T32	0	42941	0	0
T33	0	162016	0	0
T34	0	42685	0	0
T35	0	136045	0	0
T36	0	104347	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	691875694	117502	0	0
T6	119507	15683	0	0
T7	20554	0	0	0
T8	509669	0	0	0
T9	305214	0	0	0
T10	7269	0	0	0
T11	44760	0	0	0
T12	211021	0	0	0
T13	209845	0	0	0
T14	8883	0	0	0
T15	882551	0	0	0
T16	0	15750	0	0
T34	0	4598	0	0
T82	0	8839	0	0
T83	0	14759	0	0
T84	0	4276	0	0
T85	0	7003	0	0
T86	0	3909	0	0
T87	0	9278	0	0
T88	0	16355	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	691875694	102748	0	0
T6	119507	12967	0	0
T7	20554	0	0	0
T8	509669	0	0	0
T9	305214	0	0	0
T10	7269	0	0	0
T11	44760	0	0	0
T12	211021	0	0	0
T13	209845	0	0	0
T14	8883	0	0	0
T15	882551	0	0	0
T16	0	13784	0	0
T34	0	3704	0	0
T82	0	8466	0	0
T83	0	13260	0	0
T84	0	3633	0	0
T85	0	5916	0	0
T86	0	3509	0	0
T87	0	8342	0	0
T88	0	14121	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	691875694	103131	0	0
T6	119507	13148	0	0
T7	20554	0	0	0
T8	509669	0	0	0
T9	305214	0	0	0
T10	7269	0	0	0
T11	44760	0	0	0
T12	211021	0	0	0
T13	209845	0	0	0
T14	8883	0	0	0
T15	882551	0	0	0
T16	0	14195	0	0
T34	0	4127	0	0
T82	0	8253	0	0
T83	0	13061	0	0
T84	0	3618	0	0
T85	0	5971	0	0
T86	0	3441	0	0
T87	0	8223	0	0
T88	0	14182	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	691875694	117134	0	0
T6	119507	15132	0	0
T7	20554	0	0	0
T8	509669	0	0	0
T9	305214	0	0	0
T10	7269	0	0	0
T11	44760	0	0	0
T12	211021	0	0	0
T13	209845	0	0	0
T14	8883	0	0	0
T15	882551	0	0	0
T16	0	15208	0	0
T34	0	4645	0	0
T82	0	9330	0	0
T83	0	14757	0	0
T84	0	4280	0	0
T85	0	6831	0	0
T86	0	3805	0	0
T87	0	9233	0	0
T88	0	16833	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	691875694	102471	0	0
T6	119507	13500	0	0
T7	20554	0	0	0
T8	509669	0	0	0
T9	305214	0	0	0
T10	7269	0	0	0
T11	44760	0	0	0
T12	211021	0	0	0
T13	209845	0	0	0
T14	8883	0	0	0
T15	882551	0	0	0
T16	0	13813	0	0
T34	0	3548	0	0
T82	0	8195	0	0
T83	0	12832	0	0
T84	0	3582	0	0
T85	0	6018	0	0
T86	0	2786	0	0
T87	0	8102	0	0
T88	0	14960	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	691875694	118704	0	0
T6	119507	15484	0	0
T7	20554	0	0	0
T8	509669	0	0	0
T9	305214	0	0	0
T10	7269	0	0	0
T11	44760	0	0	0
T12	211021	0	0	0
T13	209845	0	0	0
T14	8883	0	0	0
T15	882551	0	0	0
T16	0	15592	0	0
T34	0	4773	0	0
T82	0	9799	0	0
T83	0	15259	0	0
T84	0	4442	0	0
T85	0	6412	0	0
T86	0	3530	0	0
T87	0	9467	0	0
T88	0	17072	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	691875694	102045	0	0
T6	119507	13448	0	0
T7	20554	0	0	0
T8	509669	0	0	0
T9	305214	0	0	0
T10	7269	0	0	0
T11	44760	0	0	0
T12	211021	0	0	0
T13	209845	0	0	0
T14	8883	0	0	0
T15	882551	0	0	0
T16	0	13616	0	0
T34	0	4317	0	0
T82	0	8323	0	0
T83	0	12649	0	0
T84	0	3489	0	0
T85	0	5433	0	0
T86	0	3340	0	0
T87	0	7966	0	0
T88	0	14332	0	0