Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	403626	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4958133	1		T1	202		T2	204		T3	159946

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1317954	1		T1	29		T2	36		T3	42707
values[0x0]	1895088	1		T1	139		T2	126		T3	60610
values[0x1]	2148717	1		T1	133		T2	145		T3	69454

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	178678	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5183081	1		T1	227		T2	225		T3	167098

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19191	1		T1	1		T3	734		T4	780
valid_sources[0x01]	21027	1		T3	514		T4	772		T5	1
valid_sources[0x02]	22377	1		T1	3		T3	689		T4	862
valid_sources[0x03]	20868	1		T1	1		T2	4		T3	869
valid_sources[0x04]	19073	1		T1	3		T3	430		T4	777
valid_sources[0x05]	21102	1		T2	1		T3	866		T4	909
valid_sources[0x06]	21060	1		T1	1		T3	986		T4	814
valid_sources[0x07]	22488	1		T3	1101		T4	747		T13	208
valid_sources[0x08]	20723	1		T3	143		T4	881		T8	2
valid_sources[0x09]	19992	1		T1	3		T3	523		T4	852
valid_sources[0x0a]	22080	1		T3	514		T4	875		T13	193
valid_sources[0x0b]	21215	1		T3	570		T4	838		T12	6
valid_sources[0x0c]	20503	1		T1	1		T3	691		T4	867
valid_sources[0x0d]	21387	1		T3	329		T4	835		T7	4
valid_sources[0x0e]	20319	1		T1	1		T3	675		T4	781
valid_sources[0x0f]	22178	1		T3	183		T4	780		T7	7
valid_sources[0x10]	21664	1		T1	2		T3	389		T4	823
valid_sources[0x11]	22086	1		T2	1		T3	206		T4	766
valid_sources[0x12]	22905	1		T3	1577		T4	819		T5	1
valid_sources[0x13]	19772	1		T1	4		T2	23		T3	446
valid_sources[0x14]	22104	1		T3	579		T4	797		T12	2
valid_sources[0x15]	21787	1		T3	941		T4	779		T9	2
valid_sources[0x16]	19506	1		T3	708		T4	813		T8	8
valid_sources[0x17]	20643	1		T1	2		T3	568		T4	806
valid_sources[0x18]	20326	1		T1	1		T3	467		T4	812
valid_sources[0x19]	20990	1		T1	3		T3	415		T4	920
valid_sources[0x1a]	20001	1		T3	402		T4	823		T8	12
valid_sources[0x1b]	19799	1		T1	1		T2	7		T3	612
valid_sources[0x1c]	20911	1		T3	1016		T4	752		T8	2
valid_sources[0x1d]	20959	1		T3	634		T4	760		T12	3
valid_sources[0x1e]	21564	1		T1	4		T3	394		T4	748
valid_sources[0x1f]	21149	1		T1	1		T3	667		T4	851
valid_sources[0x20]	19514	1		T3	1263		T4	775		T8	4
valid_sources[0x21]	21051	1		T1	1		T3	685		T4	859
valid_sources[0x22]	20580	1		T3	1159		T4	688		T8	2
valid_sources[0x23]	20226	1		T1	3		T3	642		T4	805
valid_sources[0x24]	22015	1		T1	2		T3	742		T4	830
valid_sources[0x25]	20926	1		T3	836		T4	875		T8	1
valid_sources[0x26]	17925	1		T1	1		T3	266		T4	844
valid_sources[0x27]	21336	1		T1	1		T3	576		T4	781
valid_sources[0x28]	21930	1		T1	1		T3	908		T4	854
valid_sources[0x29]	22171	1		T1	1		T3	373		T4	840
valid_sources[0x2a]	21731	1		T1	2		T3	1070		T4	965
valid_sources[0x2b]	21531	1		T3	329		T4	803		T8	2
valid_sources[0x2c]	20302	1		T1	1		T3	886		T4	886
valid_sources[0x2d]	19630	1		T1	1		T3	650		T4	788
valid_sources[0x2e]	21663	1		T3	1352		T4	854		T7	9
valid_sources[0x2f]	20680	1		T1	1		T3	672		T4	863
valid_sources[0x30]	21824	1		T1	1		T3	836		T4	840
valid_sources[0x31]	18674	1		T3	345		T4	798		T7	11
valid_sources[0x32]	21350	1		T1	2		T3	616		T4	790
valid_sources[0x33]	20837	1		T1	3		T3	1024		T4	880
valid_sources[0x34]	19677	1		T2	8		T3	769		T4	768
valid_sources[0x35]	22791	1		T3	1001		T4	822		T6	1
valid_sources[0x36]	20766	1		T1	2		T3	733		T4	765
valid_sources[0x37]	22770	1		T3	805		T4	856		T13	191
valid_sources[0x38]	19836	1		T1	1		T3	521		T4	887
valid_sources[0x39]	22038	1		T1	1		T3	439		T4	732
valid_sources[0x3a]	18442	1		T1	2		T3	1146		T4	781
valid_sources[0x3b]	20959	1		T1	1		T3	183		T4	788
valid_sources[0x3c]	19987	1		T1	1		T3	264		T4	762
valid_sources[0x3d]	21743	1		T2	2		T3	669		T4	790
valid_sources[0x3e]	23246	1		T1	2		T3	1024		T4	859
valid_sources[0x3f]	19026	1		T1	1		T3	123		T4	826
valid_sources[0x40]	20264	1		T2	7		T3	913		T4	774
valid_sources[0x41]	18788	1		T1	3		T3	337		T4	763
valid_sources[0x42]	21884	1		T3	1059		T4	845		T7	2
valid_sources[0x43]	19751	1		T1	2		T3	504		T4	764
valid_sources[0x44]	20749	1		T1	3		T3	921		T4	820
valid_sources[0x45]	21063	1		T3	726		T4	816		T7	7
valid_sources[0x46]	22174	1		T1	1		T3	1173		T4	793
valid_sources[0x47]	18309	1		T1	1		T3	255		T4	794
valid_sources[0x48]	20920	1		T1	5		T3	447		T4	666
valid_sources[0x49]	19954	1		T1	1		T3	585		T4	794
valid_sources[0x4a]	21227	1		T1	1		T3	776		T4	839
valid_sources[0x4b]	20115	1		T3	473		T4	786		T8	1
valid_sources[0x4c]	19594	1		T1	3		T3	522		T4	777
valid_sources[0x4d]	20710	1		T1	1		T3	555		T4	790
valid_sources[0x4e]	21985	1		T2	17		T3	340		T4	799
valid_sources[0x4f]	18921	1		T1	2		T3	646		T4	735
valid_sources[0x50]	21893	1		T1	3		T3	830		T4	753
valid_sources[0x51]	20555	1		T1	4		T3	756		T4	813
valid_sources[0x52]	21160	1		T3	728		T4	768		T8	1
valid_sources[0x53]	19710	1		T1	2		T3	728		T4	934
valid_sources[0x54]	19022	1		T1	5		T3	481		T4	949
valid_sources[0x55]	21349	1		T1	1		T3	719		T4	765
valid_sources[0x56]	19544	1		T1	2		T2	4		T3	670
valid_sources[0x57]	20491	1		T2	1		T3	432		T4	922
valid_sources[0x58]	23396	1		T3	937		T4	833		T7	3
valid_sources[0x59]	20223	1		T1	1		T3	323		T4	859
valid_sources[0x5a]	23189	1		T1	2		T3	1005		T4	884
valid_sources[0x5b]	22712	1		T1	1		T3	440		T4	842
valid_sources[0x5c]	20455	1		T1	1		T3	731		T4	831
valid_sources[0x5d]	22249	1		T1	2		T3	642		T4	865
valid_sources[0x5e]	22053	1		T1	1		T3	386		T4	832
valid_sources[0x5f]	21568	1		T1	2		T3	924		T4	845
valid_sources[0x60]	19265	1		T3	394		T4	723		T12	1
valid_sources[0x61]	19833	1		T1	1		T3	814		T4	796
valid_sources[0x62]	21414	1		T3	784		T4	703		T5	1
valid_sources[0x63]	20405	1		T1	1		T3	574		T4	740
valid_sources[0x64]	23044	1		T1	2		T3	833		T4	842
valid_sources[0x65]	22065	1		T3	776		T4	857		T7	1
valid_sources[0x66]	20731	1		T2	15		T3	927		T4	727
valid_sources[0x67]	19862	1		T3	640		T4	804		T12	5
valid_sources[0x68]	21345	1		T1	1		T3	467		T4	895
valid_sources[0x69]	20425	1		T1	3		T3	1132		T4	744
valid_sources[0x6a]	21452	1		T2	10		T3	481		T4	739
valid_sources[0x6b]	19265	1		T1	2		T3	630		T4	807
valid_sources[0x6c]	20550	1		T3	197		T4	798		T7	3
valid_sources[0x6d]	21443	1		T1	3		T3	431		T4	838
valid_sources[0x6e]	19596	1		T3	712		T4	764		T10	1
valid_sources[0x6f]	23221	1		T1	1		T3	632		T4	789
valid_sources[0x70]	20376	1		T1	2		T3	769		T4	803
valid_sources[0x71]	22845	1		T1	3		T3	492		T4	870
valid_sources[0x72]	21429	1		T1	1		T3	723		T4	911
valid_sources[0x73]	22375	1		T1	1		T3	580		T4	917
valid_sources[0x74]	19928	1		T3	549		T4	852		T13	207
valid_sources[0x75]	20778	1		T1	1		T3	815		T4	823
valid_sources[0x76]	22246	1		T1	4		T3	271		T4	886
valid_sources[0x77]	21338	1		T3	549		T4	885		T12	3
valid_sources[0x78]	21695	1		T1	1		T3	982		T4	788
valid_sources[0x79]	21881	1		T1	1		T3	1260		T4	863
valid_sources[0x7a]	23485	1		T1	1		T3	589		T4	740
valid_sources[0x7b]	20918	1		T1	2		T3	841		T4	927
valid_sources[0x7c]	20570	1		T1	1		T3	762		T4	852
valid_sources[0x7d]	20269	1		T2	12		T3	335		T4	821
valid_sources[0x7e]	18909	1		T1	1		T2	5		T3	677
valid_sources[0x7f]	21504	1		T3	509		T4	873		T8	3
valid_sources[0x80]	22745	1		T1	2		T3	480		T4	729

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1236573

1

T1

12

T2

16

T3

40116

values[0x0]

all_enables

biggest_size

1861686

1

T1

94

T2

91

T3

59681

values[0x1]

all_enables

biggest_size

1859874

1

T1

96

T2

97

T3

60149