Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	793721619	5930799	0	0
wdog_bark_thold_rd_A	793721619	95619	0	0
wdog_bite_thold_rd_A	793721619	84049	0	0
wdog_ctrl_rd_A	793721619	84411	0	0
wdog_regwen_rd_A	793721619	96819	0	0
wkup_ctrl_rd_A	793721619	83779	0	0
wkup_thold_hi_rd_A	793721619	96556	0	0
wkup_thold_lo_rd_A	793721619	83920	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793721619	5930799	0	0
T3	556544	195035	0	0
T4	814267	234389	0	0
T5	33422	0	0	0
T6	509953	0	0	0
T7	137784	0	0	0
T8	113944	0	0	0
T9	14788	0	0	0
T10	749154	0	0	0
T11	723556	0	0	0
T12	401237	0	0	0
T13	0	54815	0	0
T29	0	82924	0	0
T38	0	111329	0	0
T39	0	101071	0	0
T40	0	131813	0	0
T41	0	107404	0	0
T42	0	189861	0	0
T43	0	112364	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793721619	95619	0	0
T29	344565	4334	0	0
T49	0	20196	0	0
T50	0	3555	0	0
T95	0	22877	0	0
T97	0	3580	0	0
T98	0	3091	0	0
T99	0	1155	0	0
T100	0	2082	0	0
T101	0	1268	0	0
T102	0	17514	0	0
T103	43557	0	0	0
T104	11390	0	0	0
T105	63805	0	0	0
T106	56616	0	0	0
T107	229371	0	0	0
T108	492599	0	0	0
T109	39963	0	0	0
T110	263288	0	0	0
T111	177209	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793721619	84049	0	0
T29	344565	3785	0	0
T49	0	17814	0	0
T50	0	3021	0	0
T95	0	19929	0	0
T97	0	3398	0	0
T98	0	3003	0	0
T99	0	1031	0	0
T100	0	1967	0	0
T101	0	1214	0	0
T102	0	14798	0	0
T103	43557	0	0	0
T104	11390	0	0	0
T105	63805	0	0	0
T106	56616	0	0	0
T107	229371	0	0	0
T108	492599	0	0	0
T109	39963	0	0	0
T110	263288	0	0	0
T111	177209	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793721619	84411	0	0
T29	344565	3661	0	0
T49	0	17419	0	0
T50	0	3148	0	0
T95	0	19843	0	0
T97	0	3198	0	0
T98	0	2916	0	0
T99	0	1061	0	0
T100	0	1997	0	0
T101	0	1357	0	0
T102	0	15445	0	0
T103	43557	0	0	0
T104	11390	0	0	0
T105	63805	0	0	0
T106	56616	0	0	0
T107	229371	0	0	0
T108	492599	0	0	0
T109	39963	0	0	0
T110	263288	0	0	0
T111	177209	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793721619	96819	0	0
T29	344565	4338	0	0
T49	0	19592	0	0
T50	0	3747	0	0
T95	0	23379	0	0
T97	0	3851	0	0
T98	0	3055	0	0
T99	0	1206	0	0
T100	0	2057	0	0
T101	0	1549	0	0
T102	0	17485	0	0
T103	43557	0	0	0
T104	11390	0	0	0
T105	63805	0	0	0
T106	56616	0	0	0
T107	229371	0	0	0
T108	492599	0	0	0
T109	39963	0	0	0
T110	263288	0	0	0
T111	177209	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793721619	83779	0	0
T29	344565	3861	0	0
T49	0	17593	0	0
T50	0	2939	0	0
T95	0	20041	0	0
T97	0	3270	0	0
T98	0	2908	0	0
T99	0	1111	0	0
T100	0	1940	0	0
T101	0	1175	0	0
T102	0	15146	0	0
T103	43557	0	0	0
T104	11390	0	0	0
T105	63805	0	0	0
T106	56616	0	0	0
T107	229371	0	0	0
T108	492599	0	0	0
T109	39963	0	0	0
T110	263288	0	0	0
T111	177209	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793721619	96556	0	0
T29	344565	4644	0	0
T49	0	20519	0	0
T50	0	3580	0	0
T95	0	24046	0	0
T97	0	3882	0	0
T98	0	3242	0	0
T99	0	1091	0	0
T100	0	2218	0	0
T101	0	1213	0	0
T102	0	16677	0	0
T103	43557	0	0	0
T104	11390	0	0	0
T105	63805	0	0	0
T106	56616	0	0	0
T107	229371	0	0	0
T108	492599	0	0	0
T109	39963	0	0	0
T110	263288	0	0	0
T111	177209	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793721619	83920	0	0
T29	344565	3680	0	0
T49	0	18367	0	0
T50	0	3021	0	0
T95	0	19943	0	0
T97	0	3104	0	0
T98	0	2509	0	0
T99	0	1011	0	0
T100	0	1855	0	0
T101	0	1205	0	0
T102	0	15080	0	0
T103	43557	0	0	0
T104	11390	0	0	0
T105	63805	0	0	0
T106	56616	0	0	0
T107	229371	0	0	0
T108	492599	0	0	0
T109	39963	0	0	0
T110	263288	0	0	0
T111	177209	0	0	0