Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45116	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	339959	1		T1	4004		T2	14		T3	15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	96898	1		T1	1080		T2	1		T3	1
values[0x0]	136301	1		T1	1572		T2	8		T3	10
values[0x1]	151876	1		T1	1819		T2	10		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27068	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	358007	1		T1	4218		T2	16		T3	15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1082	1		T1	6		T3	2		T7	9
valid_sources[0x01]	1422	1		T1	14		T7	22		T8	3
valid_sources[0x02]	2406	1		T1	39		T7	18		T11	39
valid_sources[0x03]	1146	1		T1	2		T7	12		T8	2
valid_sources[0x04]	1223	1		T1	34		T7	29		T8	3
valid_sources[0x05]	1432	1		T1	1		T7	31		T10	1
valid_sources[0x06]	2016	1		T7	10		T10	1		T11	10
valid_sources[0x07]	1296	1		T1	50		T7	8		T11	19
valid_sources[0x08]	1902	1		T1	3		T7	22		T10	2
valid_sources[0x09]	1432	1		T1	5		T7	14		T11	23
valid_sources[0x0a]	1339	1		T1	23		T7	20		T8	3
valid_sources[0x0b]	1503	1		T1	5		T5	2		T7	15
valid_sources[0x0c]	1432	1		T1	54		T7	27		T8	2
valid_sources[0x0d]	1143	1		T1	14		T7	6		T8	1
valid_sources[0x0e]	2180	1		T1	25		T7	19		T9	1
valid_sources[0x0f]	1819	1		T1	25		T7	29		T8	4
valid_sources[0x10]	1232	1		T1	21		T7	17		T10	3
valid_sources[0x11]	1195	1		T1	23		T7	15		T8	1
valid_sources[0x12]	1428	1		T5	1		T7	8		T8	1
valid_sources[0x13]	1321	1		T1	24		T7	6		T8	1
valid_sources[0x14]	1415	1		T1	11		T7	7		T10	2
valid_sources[0x15]	1759	1		T1	11		T7	22		T11	8
valid_sources[0x16]	1251	1		T5	2		T7	13		T8	4
valid_sources[0x17]	1297	1		T1	15		T7	28		T8	1
valid_sources[0x18]	1107	1		T1	10		T7	16		T8	2
valid_sources[0x19]	1085	1		T1	11		T3	1		T7	20
valid_sources[0x1a]	1907	1		T1	79		T7	15		T10	2
valid_sources[0x1b]	1351	1		T1	2		T2	1		T7	10
valid_sources[0x1c]	1483	1		T1	1		T7	12		T8	1
valid_sources[0x1d]	2261	1		T1	29		T7	21		T9	1
valid_sources[0x1e]	1463	1		T1	1		T7	14		T8	5
valid_sources[0x1f]	1377	1		T3	1		T7	11		T8	2
valid_sources[0x20]	1336	1		T1	56		T7	24		T8	5
valid_sources[0x21]	1179	1		T1	6		T7	6		T8	1
valid_sources[0x22]	1817	1		T1	2		T2	1		T7	11
valid_sources[0x23]	1450	1		T1	68		T7	21		T10	1
valid_sources[0x24]	1630	1		T1	35		T7	14		T8	1
valid_sources[0x25]	1458	1		T1	25		T7	18		T8	1
valid_sources[0x26]	1554	1		T1	33		T3	2		T7	6
valid_sources[0x27]	1610	1		T1	16		T7	31		T10	1
valid_sources[0x28]	1924	1		T1	11		T7	5		T8	1
valid_sources[0x29]	1620	1		T1	13		T2	2		T7	14
valid_sources[0x2a]	1762	1		T1	48		T7	17		T8	1
valid_sources[0x2b]	1626	1		T1	1		T7	22		T8	1
valid_sources[0x2c]	1153	1		T1	17		T7	17		T8	2
valid_sources[0x2d]	1566	1		T1	7		T7	18		T8	1
valid_sources[0x2e]	1431	1		T1	25		T7	10		T8	5
valid_sources[0x2f]	1690	1		T7	16		T8	5		T10	2
valid_sources[0x30]	1598	1		T1	19		T7	10		T8	4
valid_sources[0x31]	1534	1		T1	3		T7	10		T10	1
valid_sources[0x32]	1879	1		T1	35		T7	25		T10	2
valid_sources[0x33]	1564	1		T1	76		T2	1		T3	1
valid_sources[0x34]	984	1		T1	14		T7	14		T8	4
valid_sources[0x35]	1750	1		T1	14		T7	9		T9	1
valid_sources[0x36]	1363	1		T5	3		T7	6		T10	3
valid_sources[0x37]	1730	1		T1	27		T7	27		T8	1
valid_sources[0x38]	1538	1		T1	8		T7	17		T11	20
valid_sources[0x39]	1767	1		T1	6		T3	3		T7	20
valid_sources[0x3a]	1298	1		T1	40		T3	1		T7	10
valid_sources[0x3b]	1451	1		T1	1		T7	17		T8	6
valid_sources[0x3c]	1490	1		T1	30		T7	10		T8	2
valid_sources[0x3d]	1199	1		T1	54		T7	26		T8	3
valid_sources[0x3e]	1343	1		T7	21		T10	2		T11	6
valid_sources[0x3f]	1747	1		T1	1		T2	1		T7	3
valid_sources[0x40]	1255	1		T1	8		T7	9		T8	1
valid_sources[0x41]	1606	1		T1	9		T7	14		T8	2
valid_sources[0x42]	1495	1		T1	80		T7	14		T8	1
valid_sources[0x43]	1323	1		T1	1		T7	21		T11	35
valid_sources[0x44]	1461	1		T1	17		T7	18		T8	3
valid_sources[0x45]	1516	1		T1	7		T7	17		T11	18
valid_sources[0x46]	1713	1		T1	2		T7	12		T8	4
valid_sources[0x47]	1444	1		T1	14		T7	14		T10	5
valid_sources[0x48]	1261	1		T1	41		T6	19		T7	16
valid_sources[0x49]	1459	1		T1	4		T7	30		T8	12
valid_sources[0x4a]	1639	1		T1	9		T7	21		T8	3
valid_sources[0x4b]	1618	1		T1	48		T3	1		T7	15
valid_sources[0x4c]	1334	1		T1	1		T7	16		T11	7
valid_sources[0x4d]	2178	1		T7	10		T10	2		T11	24
valid_sources[0x4e]	1765	1		T1	40		T7	26		T8	1
valid_sources[0x4f]	1302	1		T1	9		T7	17		T11	12
valid_sources[0x50]	1663	1		T1	3		T7	10		T8	1
valid_sources[0x51]	1959	1		T1	4		T7	32		T10	4
valid_sources[0x52]	1459	1		T1	16		T5	1		T7	10
valid_sources[0x53]	1137	1		T1	3		T7	14		T10	1
valid_sources[0x54]	1592	1		T1	5		T7	18		T10	1
valid_sources[0x55]	1440	1		T1	14		T5	2		T7	30
valid_sources[0x56]	1956	1		T1	78		T7	8		T8	2
valid_sources[0x57]	1549	1		T1	26		T7	35		T10	1
valid_sources[0x58]	1543	1		T1	8		T7	9		T8	1
valid_sources[0x59]	1669	1		T1	5		T7	16		T8	1
valid_sources[0x5a]	1459	1		T1	8		T7	41		T8	2
valid_sources[0x5b]	1632	1		T1	31		T7	8		T8	1
valid_sources[0x5c]	1258	1		T1	59		T7	18		T10	1
valid_sources[0x5d]	1606	1		T7	16		T10	1		T11	22
valid_sources[0x5e]	1540	1		T1	1		T7	6		T8	3
valid_sources[0x5f]	1344	1		T1	48		T7	10		T8	2
valid_sources[0x60]	1845	1		T1	3		T7	15		T8	1
valid_sources[0x61]	1066	1		T1	15		T7	16		T8	6
valid_sources[0x62]	1807	1		T1	24		T7	15		T8	1
valid_sources[0x63]	1565	1		T1	62		T7	10		T11	6
valid_sources[0x64]	1179	1		T1	1		T7	17		T8	2
valid_sources[0x65]	1374	1		T1	1		T7	13		T11	21
valid_sources[0x66]	1143	1		T1	12		T3	1		T7	10
valid_sources[0x67]	1045	1		T1	3		T7	25		T8	2
valid_sources[0x68]	1423	1		T1	40		T7	11		T10	12
valid_sources[0x69]	1629	1		T1	12		T7	11		T10	1
valid_sources[0x6a]	1341	1		T1	33		T7	16		T11	19
valid_sources[0x6b]	1059	1		T7	29		T11	11		T172	2
valid_sources[0x6c]	1287	1		T1	11		T7	5		T8	4
valid_sources[0x6d]	1651	1		T7	14		T8	6		T11	13
valid_sources[0x6e]	1783	1		T1	10		T7	7		T9	1
valid_sources[0x6f]	1319	1		T1	21		T7	38		T11	28
valid_sources[0x70]	1346	1		T1	28		T7	19		T8	1
valid_sources[0x71]	1440	1		T1	5		T2	2		T7	17
valid_sources[0x72]	1485	1		T7	6		T10	6		T11	7
valid_sources[0x73]	1508	1		T1	11		T5	1		T7	14
valid_sources[0x74]	1208	1		T1	1		T5	1		T7	16
valid_sources[0x75]	1732	1		T1	19		T7	14		T8	3
valid_sources[0x76]	1134	1		T1	5		T7	11		T10	1
valid_sources[0x77]	1627	1		T1	26		T7	12		T11	18
valid_sources[0x78]	1162	1		T1	11		T7	12		T11	34
valid_sources[0x79]	1512	1		T1	1		T7	17		T11	2
valid_sources[0x7a]	1899	1		T1	2		T7	11		T10	4
valid_sources[0x7b]	1739	1		T1	18		T7	13		T10	1
valid_sources[0x7c]	1458	1		T1	1		T7	7		T10	2
valid_sources[0x7d]	1468	1		T1	9		T7	9		T8	1
valid_sources[0x7e]	1091	1		T7	8		T8	2		T11	19
valid_sources[0x7f]	1657	1		T7	13		T8	3		T10	1
valid_sources[0x80]	1572	1		T1	2		T7	21		T11	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

83665

1

T1

975

T3

1

T4

1

values[0x0]

all_enables

biggest_size

128597

1

T1

1516

T2

8

T3

9

values[0x1]

all_enables

biggest_size

127697

1

T1

1513

T2

6

T3

5