Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	527031486	340907	0	0
wdog_bark_thold_rd_A	527031486	8445	0	0
wdog_bite_thold_rd_A	527031486	7315	0	0
wdog_ctrl_rd_A	527031486	7667	0	0
wdog_regwen_rd_A	527031486	8642	0	0
wkup_ctrl_rd_A	527031486	7508	0	0
wkup_thold_hi_rd_A	527031486	8200	0	0
wkup_thold_lo_rd_A	527031486	7822	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527031486	340907	0	0
T1	192436	4821	0	0
T2	48554	0	0	0
T3	14998	0	0	0
T4	4267	0	0	0
T5	22466	0	0	0
T6	24528	0	0	0
T7	211996	4372	0	0
T8	372752	0	0	0
T9	907138	0	0	0
T10	256601	0	0	0
T11	0	5733	0	0
T19	0	4231	0	0
T21	0	4686	0	0
T24	0	3196	0	0
T39	0	4031	0	0
T40	0	3785	0	0
T41	0	10486	0	0
T42	0	1422	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527031486	8445	0	0
T1	192436	353	0	0
T2	48554	0	0	0
T3	14998	0	0	0
T4	4267	0	0	0
T5	22466	0	0	0
T6	24528	0	0	0
T7	211996	528	0	0
T8	372752	0	0	0
T9	907138	0	0	0
T10	256601	0	0	0
T21	0	485	0	0
T24	0	292	0	0
T39	0	372	0	0
T80	0	418	0	0
T81	0	783	0	0
T82	0	538	0	0
T83	0	516	0	0
T84	0	66	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527031486	7315	0	0
T1	192436	225	0	0
T2	48554	0	0	0
T3	14998	0	0	0
T4	4267	0	0	0
T5	22466	0	0	0
T6	24528	0	0	0
T7	211996	415	0	0
T8	372752	0	0	0
T9	907138	0	0	0
T10	256601	0	0	0
T21	0	381	0	0
T24	0	292	0	0
T39	0	414	0	0
T80	0	353	0	0
T81	0	657	0	0
T82	0	369	0	0
T83	0	490	0	0
T84	0	75	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527031486	7667	0	0
T1	192436	243	0	0
T2	48554	0	0	0
T3	14998	0	0	0
T4	4267	0	0	0
T5	22466	0	0	0
T6	24528	0	0	0
T7	211996	400	0	0
T8	372752	0	0	0
T9	907138	0	0	0
T10	256601	0	0	0
T21	0	440	0	0
T24	0	265	0	0
T39	0	326	0	0
T80	0	346	0	0
T81	0	805	0	0
T82	0	458	0	0
T83	0	413	0	0
T84	0	80	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527031486	8642	0	0
T1	192436	352	0	0
T2	48554	0	0	0
T3	14998	0	0	0
T4	4267	0	0	0
T5	22466	0	0	0
T6	24528	0	0	0
T7	211996	470	0	0
T8	372752	0	0	0
T9	907138	0	0	0
T10	256601	0	0	0
T21	0	627	0	0
T24	0	279	0	0
T39	0	386	0	0
T80	0	434	0	0
T81	0	809	0	0
T82	0	484	0	0
T83	0	452	0	0
T84	0	105	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527031486	7508	0	0
T1	192436	191	0	0
T2	48554	0	0	0
T3	14998	0	0	0
T4	4267	0	0	0
T5	22466	0	0	0
T6	24528	0	0	0
T7	211996	335	0	0
T8	372752	0	0	0
T9	907138	0	0	0
T10	256601	0	0	0
T21	0	489	0	0
T24	0	280	0	0
T39	0	342	0	0
T80	0	418	0	0
T81	0	723	0	0
T82	0	349	0	0
T83	0	401	0	0
T84	0	99	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527031486	8200	0	0
T1	192436	269	0	0
T2	48554	0	0	0
T3	14998	0	0	0
T4	4267	0	0	0
T5	22466	0	0	0
T6	24528	0	0	0
T7	211996	402	0	0
T8	372752	0	0	0
T9	907138	0	0	0
T10	256601	0	0	0
T21	0	513	0	0
T24	0	377	0	0
T39	0	415	0	0
T80	0	429	0	0
T81	0	936	0	0
T82	0	449	0	0
T83	0	383	0	0
T84	0	114	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527031486	7822	0	0
T1	192436	234	0	0
T2	48554	0	0	0
T3	14998	0	0	0
T4	4267	0	0	0
T5	22466	0	0	0
T6	24528	0	0	0
T7	211996	412	0	0
T8	372752	0	0	0
T9	907138	0	0	0
T10	256601	0	0	0
T21	0	481	0	0
T24	0	267	0	0
T39	0	308	0	0
T80	0	409	0	0
T81	0	797	0	0
T82	0	371	0	0
T83	0	493	0	0
T84	0	99	0	0