Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42860	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	307093	1		T1	8643		T2	16		T3	18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	89639	1		T1	2455		T2	1		T3	1
values[0x0]	123632	1		T1	3387		T2	10		T3	12
values[0x1]	136682	1		T1	3721		T2	11		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26487	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	323466	1		T1	9069		T2	19		T3	18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1831	1		T1	219		T2	4		T6	22
valid_sources[0x01]	1365	1		T1	4		T6	16		T10	8
valid_sources[0x02]	1175	1		T6	19		T8	1		T10	7
valid_sources[0x03]	1410	1		T5	1		T6	21		T8	4
valid_sources[0x04]	1325	1		T1	10		T5	1		T6	20
valid_sources[0x05]	1389	1		T1	10		T6	25		T8	1
valid_sources[0x06]	1541	1		T1	142		T6	13		T10	16
valid_sources[0x07]	1361	1		T6	17		T10	12		T11	8
valid_sources[0x08]	1384	1		T1	5		T5	2		T6	18
valid_sources[0x09]	1330	1		T6	20		T8	1		T10	12
valid_sources[0x0a]	1467	1		T1	150		T6	16		T10	14
valid_sources[0x0b]	1617	1		T1	175		T5	1		T6	19
valid_sources[0x0c]	1293	1		T2	2		T6	19		T8	2
valid_sources[0x0d]	1460	1		T5	1		T6	17		T10	12
valid_sources[0x0e]	1266	1		T6	27		T8	2		T10	13
valid_sources[0x0f]	1129	1		T5	2		T6	16		T10	9
valid_sources[0x10]	1424	1		T1	161		T6	23		T8	1
valid_sources[0x11]	1257	1		T5	3		T6	9		T8	1
valid_sources[0x12]	1322	1		T5	3		T6	18		T8	4
valid_sources[0x13]	1347	1		T6	26		T10	19		T11	3
valid_sources[0x14]	1436	1		T6	20		T8	2		T10	16
valid_sources[0x15]	1514	1		T5	1		T6	19		T8	1
valid_sources[0x16]	1239	1		T6	24		T8	1		T10	15
valid_sources[0x17]	1326	1		T5	1		T6	20		T10	8
valid_sources[0x18]	1387	1		T5	2		T6	20		T8	1
valid_sources[0x19]	1394	1		T5	1		T6	18		T10	4
valid_sources[0x1a]	1325	1		T2	1		T5	1		T6	15
valid_sources[0x1b]	1266	1		T1	155		T6	24		T8	1
valid_sources[0x1c]	1273	1		T6	25		T8	1		T10	8
valid_sources[0x1d]	1224	1		T6	21		T10	17		T11	2
valid_sources[0x1e]	1427	1		T5	2		T6	23		T8	1
valid_sources[0x1f]	1518	1		T4	2		T5	2		T6	12
valid_sources[0x20]	1440	1		T5	2		T6	14		T8	2
valid_sources[0x21]	1377	1		T5	1		T6	31		T8	7
valid_sources[0x22]	1330	1		T1	1		T5	2		T6	28
valid_sources[0x23]	1513	1		T1	236		T5	1		T6	22
valid_sources[0x24]	1202	1		T1	12		T5	1		T6	15
valid_sources[0x25]	1482	1		T5	2		T6	23		T8	2
valid_sources[0x26]	1346	1		T1	1		T5	2		T6	21
valid_sources[0x27]	1186	1		T5	5		T6	24		T8	3
valid_sources[0x28]	1340	1		T5	1		T6	18		T10	17
valid_sources[0x29]	1269	1		T5	1		T6	14		T8	3
valid_sources[0x2a]	1266	1		T5	1		T6	25		T8	1
valid_sources[0x2b]	1461	1		T1	197		T6	20		T8	4
valid_sources[0x2c]	1361	1		T5	4		T6	24		T8	2
valid_sources[0x2d]	1181	1		T6	23		T8	3		T10	11
valid_sources[0x2e]	1524	1		T6	24		T7	1		T8	5
valid_sources[0x2f]	1525	1		T1	107		T6	19		T8	4
valid_sources[0x30]	1241	1		T5	1		T6	19		T10	10
valid_sources[0x31]	2077	1		T1	613		T5	1		T6	25
valid_sources[0x32]	1501	1		T1	233		T5	1		T6	20
valid_sources[0x33]	1211	1		T1	27		T4	3		T5	2
valid_sources[0x34]	1211	1		T6	19		T8	1		T10	14
valid_sources[0x35]	2010	1		T5	5		T6	16		T8	2
valid_sources[0x36]	1193	1		T5	2		T6	12		T10	13
valid_sources[0x37]	1309	1		T5	1		T6	25		T7	2
valid_sources[0x38]	1204	1		T5	4		T6	21		T10	26
valid_sources[0x39]	1601	1		T1	311		T5	1		T6	23
valid_sources[0x3a]	1585	1		T1	292		T5	2		T6	21
valid_sources[0x3b]	1228	1		T5	1		T6	15		T8	1
valid_sources[0x3c]	1106	1		T1	67		T6	21		T10	14
valid_sources[0x3d]	1497	1		T6	15		T10	5		T11	5
valid_sources[0x3e]	1625	1		T5	1		T6	23		T8	1
valid_sources[0x3f]	1436	1		T6	22		T10	6		T27	1
valid_sources[0x40]	1384	1		T5	2		T6	28		T10	8
valid_sources[0x41]	1212	1		T6	27		T8	2		T10	14
valid_sources[0x42]	1356	1		T5	2		T6	27		T8	5
valid_sources[0x43]	1544	1		T1	335		T6	18		T8	3
valid_sources[0x44]	1541	1		T5	1		T6	19		T10	5
valid_sources[0x45]	1293	1		T1	60		T2	1		T5	1
valid_sources[0x46]	1256	1		T5	1		T6	12		T10	21
valid_sources[0x47]	1415	1		T1	180		T6	33		T8	2
valid_sources[0x48]	1413	1		T6	26		T8	14		T10	17
valid_sources[0x49]	1432	1		T1	172		T5	2		T6	22
valid_sources[0x4a]	1423	1		T5	2		T6	17		T8	8
valid_sources[0x4b]	1194	1		T1	71		T5	3		T6	20
valid_sources[0x4c]	1281	1		T5	2		T6	22		T8	1
valid_sources[0x4d]	1620	1		T1	184		T6	21		T8	5
valid_sources[0x4e]	1308	1		T6	20		T10	10		T27	1
valid_sources[0x4f]	1158	1		T5	2		T6	29		T10	25
valid_sources[0x50]	1287	1		T5	1		T6	19		T8	1
valid_sources[0x51]	1184	1		T5	1		T6	16		T8	4
valid_sources[0x52]	1339	1		T5	3		T6	23		T10	19
valid_sources[0x53]	2101	1		T1	450		T5	2		T6	17
valid_sources[0x54]	1401	1		T1	1		T5	1		T6	15
valid_sources[0x55]	1283	1		T6	22		T10	8		T11	3
valid_sources[0x56]	1361	1		T1	13		T5	2		T6	21
valid_sources[0x57]	1242	1		T1	5		T5	1		T6	20
valid_sources[0x58]	1361	1		T5	4		T6	35		T8	1
valid_sources[0x59]	1318	1		T6	21		T8	2		T10	12
valid_sources[0x5a]	1220	1		T6	17		T10	12		T11	1
valid_sources[0x5b]	1190	1		T6	19		T8	6		T10	2
valid_sources[0x5c]	1378	1		T5	2		T6	26		T8	1
valid_sources[0x5d]	1179	1		T5	1		T6	31		T8	5
valid_sources[0x5e]	1095	1		T1	23		T4	1		T5	3
valid_sources[0x5f]	1309	1		T5	3		T6	15		T10	17
valid_sources[0x60]	1271	1		T5	3		T6	20		T7	3
valid_sources[0x61]	1549	1		T1	1		T5	5		T6	16
valid_sources[0x62]	1430	1		T1	74		T5	3		T6	25
valid_sources[0x63]	1725	1		T1	60		T6	21		T10	11
valid_sources[0x64]	1504	1		T6	11		T10	2		T29	2
valid_sources[0x65]	1292	1		T5	2		T6	13		T9	20
valid_sources[0x66]	2105	1		T1	490		T5	2		T6	13
valid_sources[0x67]	1693	1		T6	20		T8	2		T10	15
valid_sources[0x68]	1575	1		T1	132		T6	25		T10	8
valid_sources[0x69]	1334	1		T1	1		T5	1		T6	26
valid_sources[0x6a]	1393	1		T3	13		T5	1		T6	19
valid_sources[0x6b]	1459	1		T5	1		T6	25		T8	1
valid_sources[0x6c]	1212	1		T1	8		T6	20		T10	20
valid_sources[0x6d]	1350	1		T5	3		T6	25		T10	18
valid_sources[0x6e]	1483	1		T1	107		T5	1		T6	18
valid_sources[0x6f]	1561	1		T1	114		T6	27		T8	2
valid_sources[0x70]	1174	1		T1	61		T6	21		T8	2
valid_sources[0x71]	1380	1		T5	4		T6	24		T8	2
valid_sources[0x72]	1385	1		T1	71		T6	13		T8	1
valid_sources[0x73]	1381	1		T6	30		T8	1		T10	5
valid_sources[0x74]	1408	1		T1	3		T5	1		T6	27
valid_sources[0x75]	1380	1		T1	19		T6	23		T8	4
valid_sources[0x76]	1210	1		T6	22		T8	2		T10	11
valid_sources[0x77]	1605	1		T1	11		T6	24		T7	2
valid_sources[0x78]	1324	1		T1	3		T5	1		T6	25
valid_sources[0x79]	1327	1		T6	21		T8	4		T10	3
valid_sources[0x7a]	1169	1		T5	1		T6	17		T8	1
valid_sources[0x7b]	1555	1		T6	21		T8	1		T10	10
valid_sources[0x7c]	1898	1		T1	87		T6	29		T10	9
valid_sources[0x7d]	1115	1		T6	22		T10	10		T27	1
valid_sources[0x7e]	1374	1		T5	1		T6	19		T8	6
valid_sources[0x7f]	1278	1		T5	1		T6	13		T10	11
valid_sources[0x80]	1584	1		T6	26		T10	16		T11	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

76205

1

T1

2206

T2

1

T3

1

values[0x0]

all_enables

biggest_size

116083

1

T1

3262

T2

10

T3

9

values[0x1]

all_enables

biggest_size

114805

1

T1

3175

T2

5

T3

8