Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	539494716	301525	0	0
wdog_bark_thold_rd_A	539494716	7430	0	0
wdog_bite_thold_rd_A	539494716	6469	0	0
wdog_ctrl_rd_A	539494716	6765	0	0
wdog_regwen_rd_A	539494716	7667	0	0
wkup_ctrl_rd_A	539494716	6670	0	0
wkup_thold_hi_rd_A	539494716	6862	0	0
wkup_thold_lo_rd_A	539494716	6290	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539494716	301525	0	0
T1	372247	10369	0	0
T2	14585	0	0	0
T3	4276	0	0	0
T4	59206	0	0	0
T5	264951	0	0	0
T6	181638	4452	0	0
T7	430173	0	0	0
T8	240958	0	0	0
T9	342476	0	0	0
T10	125532	3174	0	0
T32	0	2704	0	0
T33	0	11261	0	0
T40	0	6399	0	0
T41	0	2807	0	0
T42	0	6330	0	0
T43	0	5444	0	0
T44	0	11247	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539494716	7430	0	0
T41	144122	378	0	0
T42	334042	0	0	0
T43	278080	0	0	0
T70	0	411	0	0
T71	0	253	0	0
T72	0	307	0	0
T73	0	94	0	0
T74	0	766	0	0
T75	0	653	0	0
T76	0	559	0	0
T77	0	389	0	0
T78	0	536	0	0
T79	614944	0	0	0
T80	21438	0	0	0
T81	763267	0	0	0
T82	42506	0	0	0
T83	665714	0	0	0
T84	27793	0	0	0
T85	102412	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539494716	6469	0	0
T41	144122	270	0	0
T42	334042	0	0	0
T43	278080	0	0	0
T70	0	343	0	0
T71	0	212	0	0
T72	0	254	0	0
T73	0	131	0	0
T74	0	746	0	0
T75	0	461	0	0
T76	0	517	0	0
T77	0	283	0	0
T78	0	458	0	0
T79	614944	0	0	0
T80	21438	0	0	0
T81	763267	0	0	0
T82	42506	0	0	0
T83	665714	0	0	0
T84	27793	0	0	0
T85	102412	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539494716	6765	0	0
T41	144122	278	0	0
T42	334042	0	0	0
T43	278080	0	0	0
T70	0	354	0	0
T71	0	265	0	0
T72	0	355	0	0
T73	0	63	0	0
T74	0	614	0	0
T75	0	584	0	0
T76	0	400	0	0
T77	0	354	0	0
T78	0	440	0	0
T79	614944	0	0	0
T80	21438	0	0	0
T81	763267	0	0	0
T82	42506	0	0	0
T83	665714	0	0	0
T84	27793	0	0	0
T85	102412	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539494716	7667	0	0
T41	144122	225	0	0
T42	334042	0	0	0
T43	278080	0	0	0
T70	0	446	0	0
T71	0	282	0	0
T72	0	407	0	0
T73	0	105	0	0
T74	0	754	0	0
T75	0	666	0	0
T76	0	439	0	0
T77	0	363	0	0
T78	0	646	0	0
T79	614944	0	0	0
T80	21438	0	0	0
T81	763267	0	0	0
T82	42506	0	0	0
T83	665714	0	0	0
T84	27793	0	0	0
T85	102412	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539494716	6670	0	0
T41	144122	248	0	0
T42	334042	0	0	0
T43	278080	0	0	0
T70	0	406	0	0
T71	0	236	0	0
T72	0	310	0	0
T73	0	100	0	0
T74	0	695	0	0
T75	0	529	0	0
T76	0	508	0	0
T77	0	263	0	0
T78	0	435	0	0
T79	614944	0	0	0
T80	21438	0	0	0
T81	763267	0	0	0
T82	42506	0	0	0
T83	665714	0	0	0
T84	27793	0	0	0
T85	102412	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539494716	6862	0	0
T41	144122	282	0	0
T42	334042	0	0	0
T43	278080	0	0	0
T70	0	385	0	0
T71	0	238	0	0
T72	0	292	0	0
T73	0	112	0	0
T74	0	797	0	0
T75	0	561	0	0
T76	0	437	0	0
T77	0	326	0	0
T78	0	525	0	0
T79	614944	0	0	0
T80	21438	0	0	0
T81	763267	0	0	0
T82	42506	0	0	0
T83	665714	0	0	0
T84	27793	0	0	0
T85	102412	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539494716	6290	0	0
T41	144122	292	0	0
T42	334042	0	0	0
T43	278080	0	0	0
T70	0	303	0	0
T71	0	267	0	0
T72	0	315	0	0
T73	0	72	0	0
T74	0	765	0	0
T75	0	554	0	0
T76	0	424	0	0
T77	0	239	0	0
T78	0	368	0	0
T79	614944	0	0	0
T80	21438	0	0	0
T81	763267	0	0	0
T82	42506	0	0	0
T83	665714	0	0	0
T84	27793	0	0	0
T85	102412	0	0	0