Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	17721	1		T1	498		T2	12		T3	162
bark[1]	578	1		T3	14		T18	38		T32	26
bark[2]	133	1		T27	14		T83	30		T88	14
bark[3]	525	1		T6	21		T18	21		T19	21
bark[4]	411	1		T120	100		T46	31		T169	48
bark[5]	537	1		T28	59		T45	14		T112	277
bark[6]	226	1		T10	14		T26	72		T33	21
bark[7]	263	1		T3	30		T6	21		T85	51
bark[8]	195	1		T30	14		T31	21		T32	21
bark[9]	475	1		T23	5		T138	160		T120	21
bark[10]	155	1		T14	7		T41	26		T161	14
bark[11]	485	1		T24	43		T31	21		T138	40
bark[12]	344	1		T44	47		T46	21		T112	7
bark[13]	394	1		T14	89		T26	26		T32	35
bark[14]	406	1		T3	7		T4	14		T43	21
bark[15]	359	1		T41	7		T122	21		T100	40
bark[16]	872	1		T19	26		T120	21		T46	21
bark[17]	351	1		T151	21		T116	69		T98	21
bark[18]	259	1		T3	14		T24	81		T148	21
bark[19]	253	1		T13	14		T46	42		T83	21
bark[20]	570	1		T3	5		T24	21		T112	213
bark[21]	75	1		T95	21		T126	21		T91	21
bark[22]	617	1		T32	142		T112	21		T85	126
bark[23]	130	1		T8	14		T151	30		T129	21
bark[24]	378	1		T18	26		T31	26		T32	138
bark[25]	296	1		T25	14		T95	21		T80	21
bark[26]	583	1		T23	5		T32	42		T78	192
bark[27]	461	1		T14	21		T32	35		T46	40
bark[28]	417	1		T32	85		T44	26		T42	155
bark[29]	368	1		T112	21		T169	5		T82	21
bark[30]	456	1		T6	14		T18	69		T44	21
bark[31]	496	1		T5	14		T14	105		T31	30
bark_0	4688	1		T1	70		T2	7		T3	81

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	17403	1		T1	488		T2	11		T3	157
bite[1]	287	1		T45	13		T46	42		T85	21
bite[2]	339	1		T32	26		T95	21		T76	21
bite[3]	319	1		T3	13		T31	21		T112	160
bite[4]	406	1		T18	68		T30	13		T31	21
bite[5]	209	1		T3	6		T6	21		T28	59
bite[6]	311	1		T100	21		T101	21		T147	68
bite[7]	510	1		T112	212		T122	97		T148	21
bite[8]	718	1		T41	25		T43	21		T46	31
bite[9]	92	1		T108	13		T84	49		T109	30
bite[10]	255	1		T138	159		T151	35		T110	21
bite[11]	662	1		T4	13		T8	13		T25	13
bite[12]	343	1		T23	4		T32	21		T44	21
bite[13]	450	1		T3	4		T10	13		T32	55
bite[14]	464	1		T3	13		T32	141		T151	30
bite[15]	474	1		T6	13		T31	25		T32	84
bite[16]	251	1		T161	13		T100	35		T117	13
bite[17]	547	1		T14	88		T24	4		T19	26
bite[18]	595	1		T24	21		T43	26		T42	71
bite[19]	543	1		T5	13		T6	21		T18	21
bite[20]	248	1		T44	21		T42	13		T148	63
bite[21]	318	1		T3	30		T23	4		T112	21
bite[22]	358	1		T18	38		T24	42		T120	106
bite[23]	873	1		T42	73		T120	13		T173	13
bite[24]	282	1		T46	30		T95	21		T83	30
bite[25]	121	1		T167	13		T131	13		T94	6
bite[26]	290	1		T13	13		T41	6		T75	21
bite[27]	404	1		T18	26		T14	21		T32	35
bite[28]	414	1		T14	104		T24	21		T32	137
bite[29]	120	1		T26	33		T95	21		T89	6
bite[30]	372	1		T14	6		T31	30		T44	47
bite[31]	235	1		T24	59		T19	21		T159	13
bite_0	5264	1		T1	80		T2	8		T3	90

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29857	1		T1	236		T2	19		T3	262
auto[1]	4620	1		T1	332		T3	51		T6	19

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	579	1		T33	36		T120	266		T191	9
prescale[1]	522	1		T3	2		T26	2		T32	38
prescale[2]	408	1		T18	19		T28	19		T31	32
prescale[3]	177	1		T31	2		T192	2		T122	40
prescale[4]	503	1		T23	59		T26	2		T32	59
prescale[5]	424	1		T1	2		T14	2		T32	2
prescale[6]	433	1		T1	2		T23	9		T41	2
prescale[7]	674	1		T1	215		T6	40		T24	4
prescale[8]	311	1		T26	9		T19	36		T41	2
prescale[9]	231	1		T6	24		T18	23		T23	2
prescale[10]	351	1		T1	2		T31	92		T193	9
prescale[11]	405	1		T3	2		T14	2		T43	28
prescale[12]	220	1		T28	9		T42	2		T194	9
prescale[13]	354	1		T2	9		T26	110		T192	2
prescale[14]	248	1		T6	19		T14	2		T23	2
prescale[15]	351	1		T26	2		T42	36		T73	2
prescale[16]	180	1		T1	2		T23	21		T24	2
prescale[17]	114	1		T1	2		T14	2		T26	4
prescale[18]	627	1		T3	2		T19	19		T120	2
prescale[19]	242	1		T148	28		T178	41		T169	2
prescale[20]	476	1		T6	35		T14	63		T31	25
prescale[21]	262	1		T31	2		T43	40		T85	54
prescale[22]	375	1		T12	9		T19	38		T31	2
prescale[23]	684	1		T6	19		T9	9		T23	40
prescale[24]	297	1		T1	2		T6	19		T195	9
prescale[25]	290	1		T14	19		T112	40		T95	23
prescale[26]	222	1		T14	2		T28	57		T196	9
prescale[27]	629	1		T14	57		T23	2		T31	38
prescale[28]	610	1		T18	19		T26	36		T138	136
prescale[29]	240	1		T1	2		T19	29		T31	19
prescale[30]	266	1		T3	2		T26	2		T31	2
prescale[31]	376	1		T1	2		T32	19		T197	9
prescale_0	22396	1		T1	337		T2	10		T3	305

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	22528	1		T1	442		T2	19		T3	54
auto[1]	11949	1		T1	126		T3	259		T4	12

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	34477	1		T1	568		T2	19		T3	313

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	19358	1		T1	320		T2	14		T3	176
wkup[1]	138	1		T143	21		T113	15		T144	30
wkup[2]	194	1		T23	6		T24	21		T44	21
wkup[3]	295	1		T1	30		T30	15		T14	26
wkup[4]	182	1		T80	21		T73	35		T143	21
wkup[5]	259	1		T3	8		T14	21		T43	26
wkup[6]	214	1		T26	21		T138	35		T148	21
wkup[7]	245	1		T42	48		T120	30		T124	15
wkup[8]	156	1		T1	40		T32	21		T148	21
wkup[9]	66	1		T169	6		T98	30		T114	15
wkup[10]	105	1		T76	21		T77	6		T89	21
wkup[11]	153	1		T24	6		T41	21		T33	21
wkup[12]	207	1		T112	21		T85	21		T95	30
wkup[13]	186	1		T3	15		T10	15		T18	21
wkup[14]	104	1		T3	15		T161	15		T89	21
wkup[15]	119	1		T44	21		T112	21		T107	15
wkup[16]	150	1		T24	21		T74	21		T176	15
wkup[17]	274	1		T26	21		T112	21		T148	21
wkup[18]	202	1		T14	26		T41	8		T32	21
wkup[19]	175	1		T26	21		T95	21		T80	21
wkup[20]	275	1		T6	15		T31	21		T46	42
wkup[21]	236	1		T26	44		T42	21		T46	21
wkup[22]	135	1		T18	21		T45	15		T120	21
wkup[23]	121	1		T19	26		T31	30		T122	21
wkup[24]	63	1		T44	21		T98	21		T152	21
wkup[25]	200	1		T32	27		T138	21		T143	21
wkup[26]	158	1		T18	21		T42	42		T112	8
wkup[27]	188	1		T23	6		T120	21		T148	6
wkup[28]	224	1		T5	15		T32	26		T112	21
wkup[29]	77	1		T100	21		T73	21		T75	8
wkup[30]	280	1		T3	6		T14	21		T112	21
wkup[31]	258	1		T26	44		T42	21		T83	26
wkup[32]	196	1		T138	21		T120	15		T178	26
wkup[33]	138	1		T8	15		T25	15		T167	15
wkup[34]	248	1		T112	21		T169	26		T75	21
wkup[35]	234	1		T26	8		T138	42		T120	8
wkup[36]	113	1		T100	35		T155	15		T75	21
wkup[37]	201	1		T138	21		T148	21		T149	21
wkup[38]	257	1		T14	8		T31	21		T46	31
wkup[39]	235	1		T1	30		T32	21		T140	21
wkup[40]	264	1		T18	21		T23	6		T24	21
wkup[41]	201	1		T3	30		T6	21		T122	21
wkup[42]	239	1		T14	21		T32	31		T120	26
wkup[43]	149	1		T33	21		T73	35		T75	15
wkup[44]	125	1		T14	21		T33	21		T138	21
wkup[45]	195	1		T32	35		T151	21		T146	20
wkup[46]	122	1		T1	21		T138	21		T139	21
wkup[47]	214	1		T32	21		T43	21		T112	26
wkup[48]	348	1		T1	26		T138	21		T112	21
wkup[49]	204	1		T1	21		T6	21		T18	26
wkup[50]	97	1		T28	21		T93	21		T141	40
wkup[51]	206	1		T23	21		T32	21		T120	21
wkup[52]	134	1		T28	21		T112	42		T103	21
wkup[53]	220	1		T1	30		T31	35		T32	21
wkup[54]	98	1		T112	21		T151	35		T149	21
wkup[55]	282	1		T13	15		T31	21		T32	21
wkup[56]	120	1		T24	21		T32	21		T120	21
wkup[57]	164	1		T23	21		T31	21		T32	30
wkup[58]	204	1		T4	15		T83	21		T179	15
wkup[59]	104	1		T120	26		T110	21		T146	21
wkup[60]	105	1		T28	21		T149	21		T99	21
wkup[61]	216	1		T27	15		T112	21		T169	15
wkup[62]	99	1		T14	21		T101	21		T146	21
wkup[63]	99	1		T19	21		T108	15		T150	42
wkup_0	3649	1		T1	50		T2	5		T3	63