Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.05 99.33 93.67 100.00 98.40 99.51 43.43


Total test records in report: 421
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T40 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.986870517 Aug 14 04:27:45 PM PDT 24 Aug 14 04:27:51 PM PDT 24 456941360 ps
T288 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3240169782 Aug 14 04:28:16 PM PDT 24 Aug 14 04:28:18 PM PDT 24 532595743 ps
T289 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2450346731 Aug 14 04:28:25 PM PDT 24 Aug 14 04:28:26 PM PDT 24 284640507 ps
T290 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3872018058 Aug 14 04:27:42 PM PDT 24 Aug 14 04:27:44 PM PDT 24 484224672 ps
T34 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2805717673 Aug 14 04:28:13 PM PDT 24 Aug 14 04:28:26 PM PDT 24 7420022317 ps
T291 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3178111008 Aug 14 04:28:55 PM PDT 24 Aug 14 04:28:56 PM PDT 24 531743191 ps
T35 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1258762283 Aug 14 04:28:13 PM PDT 24 Aug 14 04:28:17 PM PDT 24 4292540384 ps
T36 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.712140977 Aug 14 04:28:02 PM PDT 24 Aug 14 04:28:06 PM PDT 24 4978038669 ps
T292 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.158545429 Aug 14 04:28:17 PM PDT 24 Aug 14 04:28:18 PM PDT 24 363910333 ps
T293 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2313432828 Aug 14 04:28:27 PM PDT 24 Aug 14 04:28:28 PM PDT 24 412077860 ps
T294 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1388731048 Aug 14 04:28:32 PM PDT 24 Aug 14 04:28:33 PM PDT 24 338505461 ps
T295 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1976690227 Aug 14 04:28:18 PM PDT 24 Aug 14 04:28:20 PM PDT 24 453339356 ps
T69 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.166849367 Aug 14 04:28:19 PM PDT 24 Aug 14 04:28:21 PM PDT 24 898545217 ps
T296 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2357541078 Aug 14 04:28:40 PM PDT 24 Aug 14 04:28:41 PM PDT 24 454641983 ps
T59 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1943979855 Aug 14 04:28:27 PM PDT 24 Aug 14 04:28:30 PM PDT 24 2357446686 ps
T297 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2102075134 Aug 14 04:28:10 PM PDT 24 Aug 14 04:28:12 PM PDT 24 581965440 ps
T298 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.481172634 Aug 14 04:28:00 PM PDT 24 Aug 14 04:28:02 PM PDT 24 437415835 ps
T184 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2041562612 Aug 14 04:28:19 PM PDT 24 Aug 14 04:28:21 PM PDT 24 4565379491 ps
T299 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3923838227 Aug 14 04:28:21 PM PDT 24 Aug 14 04:28:22 PM PDT 24 465653941 ps
T300 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.614224418 Aug 14 04:28:16 PM PDT 24 Aug 14 04:28:17 PM PDT 24 500133925 ps
T301 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.306249227 Aug 14 04:28:41 PM PDT 24 Aug 14 04:28:42 PM PDT 24 4455782012 ps
T302 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3368000 Aug 14 04:28:25 PM PDT 24 Aug 14 04:28:26 PM PDT 24 448913306 ps
T70 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3788424465 Aug 14 04:28:10 PM PDT 24 Aug 14 04:28:11 PM PDT 24 752895409 ps
T60 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3790447590 Aug 14 04:28:05 PM PDT 24 Aug 14 04:28:06 PM PDT 24 2164016466 ps
T303 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1759511171 Aug 14 04:28:28 PM PDT 24 Aug 14 04:28:30 PM PDT 24 393338527 ps
T71 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3062397258 Aug 14 04:28:11 PM PDT 24 Aug 14 04:28:13 PM PDT 24 592206582 ps
T304 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2507180908 Aug 14 04:28:09 PM PDT 24 Aug 14 04:28:10 PM PDT 24 369492537 ps
T305 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3484194105 Aug 14 04:28:19 PM PDT 24 Aug 14 04:28:21 PM PDT 24 385959992 ps
T306 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1500613995 Aug 14 04:28:24 PM PDT 24 Aug 14 04:28:25 PM PDT 24 380915125 ps
T61 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.152680877 Aug 14 04:28:06 PM PDT 24 Aug 14 04:28:07 PM PDT 24 1423437650 ps
T307 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2509872795 Aug 14 04:28:14 PM PDT 24 Aug 14 04:28:15 PM PDT 24 499790622 ps
T72 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.4199360403 Aug 14 04:28:05 PM PDT 24 Aug 14 04:28:06 PM PDT 24 540819298 ps
T62 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.648077763 Aug 14 04:28:12 PM PDT 24 Aug 14 04:28:16 PM PDT 24 1363645901 ps
T63 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2436447125 Aug 14 04:27:57 PM PDT 24 Aug 14 04:27:59 PM PDT 24 1084544070 ps
T308 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3308734972 Aug 14 04:28:13 PM PDT 24 Aug 14 04:28:13 PM PDT 24 295243827 ps
T309 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1178644667 Aug 14 04:28:14 PM PDT 24 Aug 14 04:28:16 PM PDT 24 517306124 ps
T310 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2364914291 Aug 14 04:28:22 PM PDT 24 Aug 14 04:28:23 PM PDT 24 621965333 ps
T311 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3123171665 Aug 14 04:28:27 PM PDT 24 Aug 14 04:28:28 PM PDT 24 522227639 ps
T312 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1950972245 Aug 14 04:28:14 PM PDT 24 Aug 14 04:28:15 PM PDT 24 423697990 ps
T313 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3102098129 Aug 14 04:28:00 PM PDT 24 Aug 14 04:28:01 PM PDT 24 439401512 ps
T314 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.4269403327 Aug 14 04:28:24 PM PDT 24 Aug 14 04:28:26 PM PDT 24 735383475 ps
T47 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3379948191 Aug 14 04:28:19 PM PDT 24 Aug 14 04:28:20 PM PDT 24 425938841 ps
T188 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2315162020 Aug 14 04:28:13 PM PDT 24 Aug 14 04:28:28 PM PDT 24 8459809499 ps
T315 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3031678364 Aug 14 04:28:29 PM PDT 24 Aug 14 04:28:30 PM PDT 24 476042456 ps
T48 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4209889958 Aug 14 04:28:14 PM PDT 24 Aug 14 04:28:20 PM PDT 24 4012873111 ps
T316 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2613537325 Aug 14 04:28:33 PM PDT 24 Aug 14 04:28:39 PM PDT 24 4141807449 ps
T317 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1589761820 Aug 14 04:28:18 PM PDT 24 Aug 14 04:28:22 PM PDT 24 8454747425 ps
T318 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2223688304 Aug 14 04:28:23 PM PDT 24 Aug 14 04:28:24 PM PDT 24 550152037 ps
T319 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3206313166 Aug 14 04:28:03 PM PDT 24 Aug 14 04:28:06 PM PDT 24 4266445158 ps
T64 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2084748747 Aug 14 04:28:20 PM PDT 24 Aug 14 04:28:24 PM PDT 24 1410457969 ps
T320 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2950504325 Aug 14 04:28:24 PM PDT 24 Aug 14 04:28:26 PM PDT 24 455208974 ps
T321 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2369536276 Aug 14 04:28:08 PM PDT 24 Aug 14 04:28:09 PM PDT 24 277920105 ps
T322 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.349744201 Aug 14 04:28:23 PM PDT 24 Aug 14 04:28:24 PM PDT 24 575766641 ps
T65 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3652169301 Aug 14 04:28:06 PM PDT 24 Aug 14 04:28:12 PM PDT 24 3175537401 ps
T323 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3334723465 Aug 14 04:28:08 PM PDT 24 Aug 14 04:28:09 PM PDT 24 468628150 ps
T324 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2730312672 Aug 14 04:27:59 PM PDT 24 Aug 14 04:28:02 PM PDT 24 498354983 ps
T325 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1171830441 Aug 14 04:28:26 PM PDT 24 Aug 14 04:28:27 PM PDT 24 295269619 ps
T66 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1392599010 Aug 14 04:28:12 PM PDT 24 Aug 14 04:28:14 PM PDT 24 1360191585 ps
T326 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.566244502 Aug 14 04:28:29 PM PDT 24 Aug 14 04:28:30 PM PDT 24 495613812 ps
T327 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2929391427 Aug 14 04:28:21 PM PDT 24 Aug 14 04:28:28 PM PDT 24 4284052301 ps
T328 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3797476654 Aug 14 04:28:27 PM PDT 24 Aug 14 04:28:28 PM PDT 24 407768414 ps
T329 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.4023829107 Aug 14 04:27:57 PM PDT 24 Aug 14 04:27:58 PM PDT 24 267950378 ps
T67 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2821394007 Aug 14 04:28:06 PM PDT 24 Aug 14 04:28:11 PM PDT 24 2390915776 ps
T68 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3108490212 Aug 14 04:28:18 PM PDT 24 Aug 14 04:28:19 PM PDT 24 1099359834 ps
T330 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3933791773 Aug 14 04:28:28 PM PDT 24 Aug 14 04:28:28 PM PDT 24 499068488 ps
T331 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.4132755557 Aug 14 04:28:26 PM PDT 24 Aug 14 04:28:28 PM PDT 24 495340414 ps
T332 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3807842729 Aug 14 04:27:52 PM PDT 24 Aug 14 04:27:55 PM PDT 24 1258156342 ps
T333 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.652247873 Aug 14 04:28:19 PM PDT 24 Aug 14 04:28:20 PM PDT 24 313504909 ps
T334 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1056639219 Aug 14 04:28:15 PM PDT 24 Aug 14 04:28:17 PM PDT 24 932601930 ps
T49 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3006690568 Aug 14 04:27:57 PM PDT 24 Aug 14 04:27:58 PM PDT 24 834796249 ps
T335 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2423933935 Aug 14 04:28:13 PM PDT 24 Aug 14 04:28:14 PM PDT 24 378551448 ps
T189 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3106084021 Aug 14 04:28:15 PM PDT 24 Aug 14 04:28:22 PM PDT 24 4465989659 ps
T336 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2602763101 Aug 14 04:28:14 PM PDT 24 Aug 14 04:28:15 PM PDT 24 301091787 ps
T190 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3691121114 Aug 14 04:28:23 PM PDT 24 Aug 14 04:28:27 PM PDT 24 4260235756 ps
T337 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.246580210 Aug 14 04:28:12 PM PDT 24 Aug 14 04:28:13 PM PDT 24 388715610 ps
T338 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3124442983 Aug 14 04:28:31 PM PDT 24 Aug 14 04:28:32 PM PDT 24 407402554 ps
T339 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2183466792 Aug 14 04:28:09 PM PDT 24 Aug 14 04:28:10 PM PDT 24 503400545 ps
T340 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.676131595 Aug 14 04:27:56 PM PDT 24 Aug 14 04:27:57 PM PDT 24 526667200 ps
T50 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3407527129 Aug 14 04:28:12 PM PDT 24 Aug 14 04:28:13 PM PDT 24 500425076 ps
T185 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2975819424 Aug 14 04:28:06 PM PDT 24 Aug 14 04:28:09 PM PDT 24 4832703078 ps
T341 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1406284398 Aug 14 04:28:04 PM PDT 24 Aug 14 04:28:05 PM PDT 24 409292531 ps
T342 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.626273593 Aug 14 04:28:30 PM PDT 24 Aug 14 04:28:31 PM PDT 24 347974902 ps
T343 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.961900516 Aug 14 04:28:23 PM PDT 24 Aug 14 04:28:23 PM PDT 24 333662854 ps
T344 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2887044261 Aug 14 04:28:04 PM PDT 24 Aug 14 04:28:06 PM PDT 24 1894234156 ps
T186 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3728701149 Aug 14 04:28:13 PM PDT 24 Aug 14 04:28:17 PM PDT 24 4457487436 ps
T345 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1923202176 Aug 14 04:28:33 PM PDT 24 Aug 14 04:28:34 PM PDT 24 378868484 ps
T51 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1942998905 Aug 14 04:28:25 PM PDT 24 Aug 14 04:28:26 PM PDT 24 359800963 ps
T346 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1703315999 Aug 14 04:28:26 PM PDT 24 Aug 14 04:28:27 PM PDT 24 325194865 ps
T347 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1888455845 Aug 14 04:28:17 PM PDT 24 Aug 14 04:28:21 PM PDT 24 3838687875 ps
T348 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3013256931 Aug 14 04:28:20 PM PDT 24 Aug 14 04:28:21 PM PDT 24 412598109 ps
T349 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1012945139 Aug 14 04:28:13 PM PDT 24 Aug 14 04:28:14 PM PDT 24 408666761 ps
T350 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2703749278 Aug 14 04:28:11 PM PDT 24 Aug 14 04:28:11 PM PDT 24 480843603 ps
T351 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3648921685 Aug 14 04:28:08 PM PDT 24 Aug 14 04:28:09 PM PDT 24 538247463 ps
T352 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1798642403 Aug 14 04:28:09 PM PDT 24 Aug 14 04:28:10 PM PDT 24 347467737 ps
T52 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1659019456 Aug 14 04:28:30 PM PDT 24 Aug 14 04:28:33 PM PDT 24 982693774 ps
T353 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.526051148 Aug 14 04:28:34 PM PDT 24 Aug 14 04:28:36 PM PDT 24 487010515 ps
T354 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3223586479 Aug 14 04:28:15 PM PDT 24 Aug 14 04:28:16 PM PDT 24 1485900583 ps
T355 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2260596370 Aug 14 04:27:59 PM PDT 24 Aug 14 04:28:00 PM PDT 24 520166340 ps
T356 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.4266873395 Aug 14 04:28:16 PM PDT 24 Aug 14 04:28:16 PM PDT 24 309959851 ps
T357 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3969363855 Aug 14 04:28:00 PM PDT 24 Aug 14 04:28:02 PM PDT 24 784241770 ps
T358 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2796870241 Aug 14 04:28:14 PM PDT 24 Aug 14 04:28:15 PM PDT 24 451949093 ps
T359 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.4008698381 Aug 14 04:28:24 PM PDT 24 Aug 14 04:28:26 PM PDT 24 931847883 ps
T360 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1702788038 Aug 14 04:29:36 PM PDT 24 Aug 14 04:29:37 PM PDT 24 450997169 ps
T361 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3292788140 Aug 14 04:28:34 PM PDT 24 Aug 14 04:28:35 PM PDT 24 503844343 ps
T362 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1602681357 Aug 14 04:28:17 PM PDT 24 Aug 14 04:28:18 PM PDT 24 868822046 ps
T363 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2857767534 Aug 14 04:28:12 PM PDT 24 Aug 14 04:28:14 PM PDT 24 495005275 ps
T364 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1823953182 Aug 14 04:28:28 PM PDT 24 Aug 14 04:28:30 PM PDT 24 493424454 ps
T53 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4037230514 Aug 14 04:28:08 PM PDT 24 Aug 14 04:28:09 PM PDT 24 589104161 ps
T54 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.132829298 Aug 14 04:28:09 PM PDT 24 Aug 14 04:28:10 PM PDT 24 453338122 ps
T365 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3497567345 Aug 14 04:28:37 PM PDT 24 Aug 14 04:28:38 PM PDT 24 430267068 ps
T366 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1297243394 Aug 14 04:28:36 PM PDT 24 Aug 14 04:28:38 PM PDT 24 2169786341 ps
T367 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2057447920 Aug 14 04:28:30 PM PDT 24 Aug 14 04:28:31 PM PDT 24 348859875 ps
T368 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3446260528 Aug 14 04:28:10 PM PDT 24 Aug 14 04:28:11 PM PDT 24 307453774 ps
T369 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2180669040 Aug 14 04:28:18 PM PDT 24 Aug 14 04:28:19 PM PDT 24 489360176 ps
T370 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1747413548 Aug 14 04:27:55 PM PDT 24 Aug 14 04:27:56 PM PDT 24 423698680 ps
T371 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3090523480 Aug 14 04:28:11 PM PDT 24 Aug 14 04:28:13 PM PDT 24 729080811 ps
T372 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1672089777 Aug 14 04:27:59 PM PDT 24 Aug 14 04:28:00 PM PDT 24 332537567 ps
T373 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3761091160 Aug 14 04:28:03 PM PDT 24 Aug 14 04:28:03 PM PDT 24 324489914 ps
T374 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.998425875 Aug 14 04:28:19 PM PDT 24 Aug 14 04:28:19 PM PDT 24 409607863 ps
T375 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1405347326 Aug 14 04:28:22 PM PDT 24 Aug 14 04:28:23 PM PDT 24 324699093 ps
T376 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1235998456 Aug 14 04:28:32 PM PDT 24 Aug 14 04:28:33 PM PDT 24 476787906 ps
T377 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2484662692 Aug 14 04:28:28 PM PDT 24 Aug 14 04:28:30 PM PDT 24 379481481 ps
T187 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.897767589 Aug 14 04:28:19 PM PDT 24 Aug 14 04:28:23 PM PDT 24 7743584605 ps
T378 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3745924156 Aug 14 04:28:12 PM PDT 24 Aug 14 04:28:13 PM PDT 24 480645494 ps
T379 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1427415835 Aug 14 04:28:16 PM PDT 24 Aug 14 04:28:18 PM PDT 24 419751181 ps
T55 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3194071344 Aug 14 04:28:10 PM PDT 24 Aug 14 04:28:11 PM PDT 24 367071952 ps
T380 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3955600379 Aug 14 04:27:45 PM PDT 24 Aug 14 04:27:46 PM PDT 24 309868006 ps
T381 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.193504357 Aug 14 04:28:23 PM PDT 24 Aug 14 04:28:24 PM PDT 24 358673081 ps
T382 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.4124610003 Aug 14 04:28:21 PM PDT 24 Aug 14 04:28:22 PM PDT 24 438377792 ps
T383 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.515662899 Aug 14 04:28:09 PM PDT 24 Aug 14 04:28:13 PM PDT 24 1779968539 ps
T56 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.525205791 Aug 14 04:28:16 PM PDT 24 Aug 14 04:28:23 PM PDT 24 11783288595 ps
T384 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1544401157 Aug 14 04:28:20 PM PDT 24 Aug 14 04:28:21 PM PDT 24 1324861678 ps
T385 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2321530718 Aug 14 04:28:27 PM PDT 24 Aug 14 04:28:28 PM PDT 24 1330357883 ps
T386 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.332582353 Aug 14 04:28:22 PM PDT 24 Aug 14 04:28:23 PM PDT 24 454799141 ps
T57 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.4241535073 Aug 14 04:28:24 PM PDT 24 Aug 14 04:28:26 PM PDT 24 394186706 ps
T387 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3266695626 Aug 14 04:28:02 PM PDT 24 Aug 14 04:28:03 PM PDT 24 372705890 ps
T388 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2365479775 Aug 14 04:28:21 PM PDT 24 Aug 14 04:28:23 PM PDT 24 383010088 ps
T389 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2342195331 Aug 14 04:28:01 PM PDT 24 Aug 14 04:28:03 PM PDT 24 346540179 ps
T390 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1429458843 Aug 14 04:28:22 PM PDT 24 Aug 14 04:28:24 PM PDT 24 435257881 ps
T391 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.522352199 Aug 14 04:28:45 PM PDT 24 Aug 14 04:28:45 PM PDT 24 326517591 ps
T392 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.84757439 Aug 14 04:28:26 PM PDT 24 Aug 14 04:28:27 PM PDT 24 437597296 ps
T58 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2903690145 Aug 14 04:27:46 PM PDT 24 Aug 14 04:27:46 PM PDT 24 451286280 ps
T393 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.4198522474 Aug 14 04:28:24 PM PDT 24 Aug 14 04:28:24 PM PDT 24 557248910 ps
T394 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1735854145 Aug 14 04:28:24 PM PDT 24 Aug 14 04:28:26 PM PDT 24 561453049 ps
T395 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2953122422 Aug 14 04:28:14 PM PDT 24 Aug 14 04:28:15 PM PDT 24 561621636 ps
T396 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3156070850 Aug 14 04:28:26 PM PDT 24 Aug 14 04:28:28 PM PDT 24 333474289 ps
T397 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3303171374 Aug 14 04:28:07 PM PDT 24 Aug 14 04:28:08 PM PDT 24 321202811 ps
T398 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2691224775 Aug 14 04:28:07 PM PDT 24 Aug 14 04:28:09 PM PDT 24 431694994 ps
T399 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.896444970 Aug 14 04:28:31 PM PDT 24 Aug 14 04:28:32 PM PDT 24 493908472 ps
T400 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2061874741 Aug 14 04:28:26 PM PDT 24 Aug 14 04:28:28 PM PDT 24 451831273 ps
T401 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.382536576 Aug 14 04:28:33 PM PDT 24 Aug 14 04:28:39 PM PDT 24 296428378 ps
T402 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3024957684 Aug 14 04:28:23 PM PDT 24 Aug 14 04:28:24 PM PDT 24 1135741590 ps
T403 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2769895647 Aug 14 04:28:10 PM PDT 24 Aug 14 04:28:16 PM PDT 24 3874667788 ps
T404 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2112897878 Aug 14 04:28:08 PM PDT 24 Aug 14 04:28:10 PM PDT 24 590028109 ps
T405 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.478965377 Aug 14 04:28:27 PM PDT 24 Aug 14 04:28:28 PM PDT 24 450545631 ps
T406 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4225354850 Aug 14 04:28:17 PM PDT 24 Aug 14 04:28:18 PM PDT 24 283748735 ps
T407 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.641301269 Aug 14 04:28:01 PM PDT 24 Aug 14 04:28:02 PM PDT 24 391277853 ps
T408 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3421372629 Aug 14 04:28:28 PM PDT 24 Aug 14 04:28:30 PM PDT 24 2279862141 ps
T409 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3529339839 Aug 14 04:28:09 PM PDT 24 Aug 14 04:28:10 PM PDT 24 332719056 ps
T410 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3646624888 Aug 14 04:28:26 PM PDT 24 Aug 14 04:28:34 PM PDT 24 4183680883 ps
T411 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4012844690 Aug 14 04:28:22 PM PDT 24 Aug 14 04:28:25 PM PDT 24 4173692119 ps
T412 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1516118668 Aug 14 04:28:27 PM PDT 24 Aug 14 04:28:28 PM PDT 24 345031156 ps
T413 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.85470038 Aug 14 04:28:28 PM PDT 24 Aug 14 04:28:29 PM PDT 24 524836433 ps
T414 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.91034525 Aug 14 04:28:42 PM PDT 24 Aug 14 04:28:43 PM PDT 24 479914812 ps
T415 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2769529417 Aug 14 04:28:12 PM PDT 24 Aug 14 04:28:16 PM PDT 24 7686277894 ps
T416 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4100891003 Aug 14 04:28:30 PM PDT 24 Aug 14 04:28:32 PM PDT 24 428309863 ps
T417 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3148721856 Aug 14 04:28:18 PM PDT 24 Aug 14 04:28:20 PM PDT 24 376566168 ps
T418 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3093215440 Aug 14 04:28:10 PM PDT 24 Aug 14 04:28:11 PM PDT 24 369815007 ps
T419 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2044924573 Aug 14 04:28:08 PM PDT 24 Aug 14 04:28:11 PM PDT 24 468949265 ps
T420 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3824931919 Aug 14 04:28:32 PM PDT 24 Aug 14 04:28:33 PM PDT 24 394697497 ps
T421 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3560459825 Aug 14 04:28:05 PM PDT 24 Aug 14 04:28:06 PM PDT 24 322884153 ps

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2627188782
Short name T3
Test name
Test status
Simulation time 2995927254 ps
CPU time 18.32 seconds
Started Aug 14 04:31:38 PM PDT 24
Finished Aug 14 04:31:57 PM PDT 24
Peak memory 199196 kb
Host smart-596d86cd-71af-4cc7-8fe0-ee125748b7cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627188782 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2627188782
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1592803221
Short name T31
Test name
Test status
Simulation time 9325549320 ps
CPU time 35.38 seconds
Started Aug 14 04:32:09 PM PDT 24
Finished Aug 14 04:32:44 PM PDT 24
Peak memory 206936 kb
Host smart-a3e1ce37-185b-4a00-87f9-5cd28d4a495d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592803221 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1592803221
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2805717673
Short name T34
Test name
Test status
Simulation time 7420022317 ps
CPU time 12.14 seconds
Started Aug 14 04:28:13 PM PDT 24
Finished Aug 14 04:28:26 PM PDT 24
Peak memory 198192 kb
Host smart-8716a6e1-e802-427b-ba6e-968e3ca8807d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805717673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2805717673
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3601168945
Short name T32
Test name
Test status
Simulation time 16137135053 ps
CPU time 44.56 seconds
Started Aug 14 04:31:29 PM PDT 24
Finished Aug 14 04:32:14 PM PDT 24
Peak memory 214800 kb
Host smart-b37fef12-5355-4e5f-b229-9db2e89eea3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601168945 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3601168945
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1809207801
Short name T6
Test name
Test status
Simulation time 132848133526 ps
CPU time 89.85 seconds
Started Aug 14 04:31:20 PM PDT 24
Finished Aug 14 04:32:50 PM PDT 24
Peak memory 192100 kb
Host smart-d30f6c56-e915-437d-986b-45c1a5de6d30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809207801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1809207801
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4037230514
Short name T53
Test name
Test status
Simulation time 589104161 ps
CPU time 0.93 seconds
Started Aug 14 04:28:08 PM PDT 24
Finished Aug 14 04:28:09 PM PDT 24
Peak memory 194176 kb
Host smart-a1511c25-64a2-4574-b4ec-efbfef41ce22
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037230514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.4037230514
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1124088717
Short name T44
Test name
Test status
Simulation time 129640712187 ps
CPU time 192.94 seconds
Started Aug 14 04:31:47 PM PDT 24
Finished Aug 14 04:35:00 PM PDT 24
Peak memory 198452 kb
Host smart-db67f899-2d47-4587-acbe-c1118a331eac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124088717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1124088717
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3275711345
Short name T92
Test name
Test status
Simulation time 46957376660 ps
CPU time 40.73 seconds
Started Aug 14 04:31:27 PM PDT 24
Finished Aug 14 04:32:08 PM PDT 24
Peak memory 192764 kb
Host smart-3db22e3f-d28e-47a7-bf23-34eed4dd56ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275711345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3275711345
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1640032430
Short name T16
Test name
Test status
Simulation time 7502168473 ps
CPU time 11.58 seconds
Started Aug 14 04:31:30 PM PDT 24
Finished Aug 14 04:31:41 PM PDT 24
Peak memory 216156 kb
Host smart-7d8945f5-063a-48f1-99b4-5d37a6ad08b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640032430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1640032430
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2215477254
Short name T90
Test name
Test status
Simulation time 231599048987 ps
CPU time 157.03 seconds
Started Aug 14 04:31:54 PM PDT 24
Finished Aug 14 04:34:31 PM PDT 24
Peak memory 192100 kb
Host smart-9099091a-483f-41be-92d7-8ad0e7c0e484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215477254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2215477254
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3228251941
Short name T83
Test name
Test status
Simulation time 63139728893 ps
CPU time 100.89 seconds
Started Aug 14 04:31:43 PM PDT 24
Finished Aug 14 04:33:24 PM PDT 24
Peak memory 193112 kb
Host smart-c7318f22-1b72-4040-897e-ddf98ead5ff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228251941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3228251941
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.53345681
Short name T79
Test name
Test status
Simulation time 31187917677 ps
CPU time 9.52 seconds
Started Aug 14 04:31:35 PM PDT 24
Finished Aug 14 04:31:45 PM PDT 24
Peak memory 192272 kb
Host smart-3beb7fd1-bd8e-4746-8619-0c83ab1d3818
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53345681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_al
l.53345681
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2356183227
Short name T98
Test name
Test status
Simulation time 72547243544 ps
CPU time 8.17 seconds
Started Aug 14 04:32:17 PM PDT 24
Finished Aug 14 04:32:25 PM PDT 24
Peak memory 193360 kb
Host smart-471662e9-80a4-4bea-8506-198b3a03e1f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356183227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2356183227
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3608134194
Short name T94
Test name
Test status
Simulation time 13944104531 ps
CPU time 20.93 seconds
Started Aug 14 04:31:37 PM PDT 24
Finished Aug 14 04:31:58 PM PDT 24
Peak memory 198680 kb
Host smart-ea1df614-e687-4524-b610-421848a0e051
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608134194 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3608134194
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.4037029019
Short name T104
Test name
Test status
Simulation time 14819196637 ps
CPU time 26.41 seconds
Started Aug 14 04:31:35 PM PDT 24
Finished Aug 14 04:32:02 PM PDT 24
Peak memory 206860 kb
Host smart-ab77ac1d-dbb4-47e5-aba5-0ab154f3f173
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037029019 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.4037029019
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.825853665
Short name T120
Test name
Test status
Simulation time 14221039655 ps
CPU time 32.38 seconds
Started Aug 14 04:32:08 PM PDT 24
Finished Aug 14 04:32:41 PM PDT 24
Peak memory 214096 kb
Host smart-0c78d185-1977-4618-9154-433942f0654a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825853665 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.825853665
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2126406441
Short name T95
Test name
Test status
Simulation time 106247910563 ps
CPU time 44.37 seconds
Started Aug 14 04:31:35 PM PDT 24
Finished Aug 14 04:32:19 PM PDT 24
Peak memory 198432 kb
Host smart-23562dad-755f-40fb-8a86-18116a4dfe0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126406441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2126406441
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1600485313
Short name T141
Test name
Test status
Simulation time 5517715282 ps
CPU time 2.56 seconds
Started Aug 14 04:32:15 PM PDT 24
Finished Aug 14 04:32:18 PM PDT 24
Peak memory 198384 kb
Host smart-c8c39276-e3ea-4557-b414-1f2fa7e83112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600485313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1600485313
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1340415171
Short name T110
Test name
Test status
Simulation time 124215623493 ps
CPU time 97.21 seconds
Started Aug 14 04:31:53 PM PDT 24
Finished Aug 14 04:33:30 PM PDT 24
Peak memory 198356 kb
Host smart-7e58ff4d-798e-4976-9b21-208d02f74b9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340415171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1340415171
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1625697865
Short name T123
Test name
Test status
Simulation time 14309178190 ps
CPU time 37.09 seconds
Started Aug 14 04:32:21 PM PDT 24
Finished Aug 14 04:32:58 PM PDT 24
Peak memory 206920 kb
Host smart-1994eac1-ac39-4155-b91e-5ca426e978b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625697865 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1625697865
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.2709841161
Short name T89
Test name
Test status
Simulation time 22121031228 ps
CPU time 42.1 seconds
Started Aug 14 04:32:28 PM PDT 24
Finished Aug 14 04:33:10 PM PDT 24
Peak memory 206916 kb
Host smart-ed161511-3d81-467a-8b90-e317385c11f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709841161 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.2709841161
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3401735941
Short name T112
Test name
Test status
Simulation time 6346191745 ps
CPU time 24.77 seconds
Started Aug 14 04:31:43 PM PDT 24
Finished Aug 14 04:32:07 PM PDT 24
Peak memory 198708 kb
Host smart-ce55c608-fbf2-494e-bcda-8081d7e9a2b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401735941 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3401735941
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.602724299
Short name T85
Test name
Test status
Simulation time 93964430885 ps
CPU time 31.52 seconds
Started Aug 14 04:31:38 PM PDT 24
Finished Aug 14 04:32:10 PM PDT 24
Peak memory 192800 kb
Host smart-cd596eb6-006e-4814-9522-b7bef9089863
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602724299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.602724299
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2794362866
Short name T143
Test name
Test status
Simulation time 10245928916 ps
CPU time 51.84 seconds
Started Aug 14 04:31:23 PM PDT 24
Finished Aug 14 04:32:16 PM PDT 24
Peak memory 214124 kb
Host smart-91054ef2-e7d2-48d1-883e-a15195d27edb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794362866 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2794362866
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.390800505
Short name T84
Test name
Test status
Simulation time 4114284210 ps
CPU time 17.18 seconds
Started Aug 14 04:32:18 PM PDT 24
Finished Aug 14 04:32:36 PM PDT 24
Peak memory 206896 kb
Host smart-144d2cb6-dbb6-422c-81a5-89146c74f220
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390800505 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.390800505
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2436447125
Short name T63
Test name
Test status
Simulation time 1084544070 ps
CPU time 1.77 seconds
Started Aug 14 04:27:57 PM PDT 24
Finished Aug 14 04:27:59 PM PDT 24
Peak memory 192896 kb
Host smart-bfcbaede-a6dc-45ac-bf5a-920f20ba874f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436447125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2436447125
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2213919952
Short name T24
Test name
Test status
Simulation time 6262798748 ps
CPU time 32.79 seconds
Started Aug 14 04:32:19 PM PDT 24
Finished Aug 14 04:32:52 PM PDT 24
Peak memory 198744 kb
Host smart-3369d114-5daa-46e3-bc6e-07eb49e2bf2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213919952 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2213919952
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3090069186
Short name T103
Test name
Test status
Simulation time 109505837021 ps
CPU time 146.89 seconds
Started Aug 14 04:32:31 PM PDT 24
Finished Aug 14 04:34:58 PM PDT 24
Peak memory 198404 kb
Host smart-d0228be6-d0ca-42b8-b79b-7ede6be817a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090069186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3090069186
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1934303981
Short name T136
Test name
Test status
Simulation time 4826615326 ps
CPU time 34 seconds
Started Aug 14 04:31:38 PM PDT 24
Finished Aug 14 04:32:12 PM PDT 24
Peak memory 198708 kb
Host smart-611ae454-8caa-44b2-a5ad-43ac5f8ae76f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934303981 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1934303981
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3608824533
Short name T149
Test name
Test status
Simulation time 22713727289 ps
CPU time 65.62 seconds
Started Aug 14 04:31:36 PM PDT 24
Finished Aug 14 04:32:42 PM PDT 24
Peak memory 206900 kb
Host smart-961bf6fa-17dd-46a6-9d29-dc50327072b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608824533 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3608824533
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.1010064368
Short name T76
Test name
Test status
Simulation time 16590414208 ps
CPU time 31.42 seconds
Started Aug 14 04:31:27 PM PDT 24
Finished Aug 14 04:31:58 PM PDT 24
Peak memory 207020 kb
Host smart-d99fca66-ed4a-42bd-b659-a346343c30f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010064368 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.1010064368
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2640645378
Short name T150
Test name
Test status
Simulation time 25582372019 ps
CPU time 28.79 seconds
Started Aug 14 04:31:43 PM PDT 24
Finished Aug 14 04:32:11 PM PDT 24
Peak memory 214240 kb
Host smart-4c22eb89-2353-486b-9d83-1f413983c75d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640645378 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2640645378
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3568929537
Short name T102
Test name
Test status
Simulation time 164663432095 ps
CPU time 21.08 seconds
Started Aug 14 04:31:55 PM PDT 24
Finished Aug 14 04:32:17 PM PDT 24
Peak memory 198588 kb
Host smart-a7a3bf13-8106-411e-aa23-900519c672c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568929537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3568929537
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1108927683
Short name T142
Test name
Test status
Simulation time 14405128306 ps
CPU time 43.14 seconds
Started Aug 14 04:31:24 PM PDT 24
Finished Aug 14 04:32:07 PM PDT 24
Peak memory 206912 kb
Host smart-49d15ad4-eaff-4ad8-81cf-4b12995aec94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108927683 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1108927683
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.59370422
Short name T81
Test name
Test status
Simulation time 308385157836 ps
CPU time 223.49 seconds
Started Aug 14 04:32:25 PM PDT 24
Finished Aug 14 04:36:08 PM PDT 24
Peak memory 192644 kb
Host smart-f44bf304-a164-4e42-b405-7b7b534aa29c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59370422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_al
l.59370422
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.1564445301
Short name T97
Test name
Test status
Simulation time 7018031133 ps
CPU time 36.52 seconds
Started Aug 14 04:31:41 PM PDT 24
Finished Aug 14 04:32:17 PM PDT 24
Peak memory 199040 kb
Host smart-dd61c242-2009-4e63-92be-c33da84588a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564445301 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.1564445301
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.571855041
Short name T137
Test name
Test status
Simulation time 99303735438 ps
CPU time 144.02 seconds
Started Aug 14 04:32:09 PM PDT 24
Finished Aug 14 04:34:33 PM PDT 24
Peak memory 193172 kb
Host smart-97ca0ee2-67c4-4cd1-ac21-240eb503fe87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571855041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.571855041
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.1392274133
Short name T14
Test name
Test status
Simulation time 6265800139 ps
CPU time 27.37 seconds
Started Aug 14 04:32:20 PM PDT 24
Finished Aug 14 04:32:47 PM PDT 24
Peak memory 198700 kb
Host smart-31b3204c-f008-43a4-abfd-dd3a7e841f9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392274133 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.1392274133
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1049701703
Short name T105
Test name
Test status
Simulation time 29800051341 ps
CPU time 12.76 seconds
Started Aug 14 04:31:42 PM PDT 24
Finished Aug 14 04:31:55 PM PDT 24
Peak memory 198392 kb
Host smart-1204cc26-58c1-43fe-904f-2aa57bd87504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049701703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1049701703
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1008039361
Short name T114
Test name
Test status
Simulation time 1925394626 ps
CPU time 9.51 seconds
Started Aug 14 04:32:15 PM PDT 24
Finished Aug 14 04:32:25 PM PDT 24
Peak memory 206832 kb
Host smart-6ef70047-a3e7-4af6-864f-52c90ed4c47f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008039361 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1008039361
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2218574252
Short name T129
Test name
Test status
Simulation time 102577475369 ps
CPU time 74.46 seconds
Started Aug 14 04:32:14 PM PDT 24
Finished Aug 14 04:33:29 PM PDT 24
Peak memory 184584 kb
Host smart-2fe4bd16-3a84-4b44-9220-577eefc83e3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218574252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2218574252
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.596913510
Short name T86
Test name
Test status
Simulation time 18928522255 ps
CPU time 11.43 seconds
Started Aug 14 04:32:25 PM PDT 24
Finished Aug 14 04:32:37 PM PDT 24
Peak memory 206932 kb
Host smart-c65d2798-5671-4d81-99f4-f1d8a3055125
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596913510 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.596913510
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.434864665
Short name T146
Test name
Test status
Simulation time 26064197554 ps
CPU time 34.88 seconds
Started Aug 14 04:32:10 PM PDT 24
Finished Aug 14 04:32:45 PM PDT 24
Peak memory 206908 kb
Host smart-34a3fcef-2d1c-4c1f-8e97-243fa0f4166b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434864665 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.434864665
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3376028792
Short name T43
Test name
Test status
Simulation time 162467098067 ps
CPU time 52 seconds
Started Aug 14 04:31:54 PM PDT 24
Finished Aug 14 04:32:46 PM PDT 24
Peak memory 198528 kb
Host smart-1f9493d4-1f6a-46a1-9b1d-f3f3b1a14da7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376028792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3376028792
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.289560804
Short name T46
Test name
Test status
Simulation time 144705925825 ps
CPU time 42.74 seconds
Started Aug 14 04:31:39 PM PDT 24
Finished Aug 14 04:32:22 PM PDT 24
Peak memory 192944 kb
Host smart-be925850-730f-41cf-821e-70a8335d5a7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289560804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.289560804
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1906663515
Short name T151
Test name
Test status
Simulation time 138327277873 ps
CPU time 176.98 seconds
Started Aug 14 04:32:07 PM PDT 24
Finished Aug 14 04:35:04 PM PDT 24
Peak memory 193016 kb
Host smart-be47162d-f3ea-4d98-998d-e559b743f4d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906663515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1906663515
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.273386205
Short name T78
Test name
Test status
Simulation time 17364409886 ps
CPU time 29.83 seconds
Started Aug 14 04:31:54 PM PDT 24
Finished Aug 14 04:32:24 PM PDT 24
Peak memory 214828 kb
Host smart-cf8df2d9-fa72-416b-be3e-3535f8cb43ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273386205 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.273386205
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.887077825
Short name T33
Test name
Test status
Simulation time 172123182174 ps
CPU time 225.13 seconds
Started Aug 14 04:31:19 PM PDT 24
Finished Aug 14 04:35:04 PM PDT 24
Peak memory 192044 kb
Host smart-db16aca3-15ea-487c-9637-3941d79ba4d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887077825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.887077825
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1602477170
Short name T42
Test name
Test status
Simulation time 4960897015 ps
CPU time 31.03 seconds
Started Aug 14 04:31:34 PM PDT 24
Finished Aug 14 04:32:05 PM PDT 24
Peak memory 198708 kb
Host smart-b82a2c44-39a5-4ec7-8c96-d0c64a8e9329
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602477170 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1602477170
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1127645861
Short name T116
Test name
Test status
Simulation time 330071475641 ps
CPU time 522.07 seconds
Started Aug 14 04:31:40 PM PDT 24
Finished Aug 14 04:40:22 PM PDT 24
Peak memory 193092 kb
Host smart-ae723083-1fe2-44fb-8c01-f8bc1393679d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127645861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1127645861
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3688730176
Short name T147
Test name
Test status
Simulation time 110805934020 ps
CPU time 44.61 seconds
Started Aug 14 04:31:49 PM PDT 24
Finished Aug 14 04:32:34 PM PDT 24
Peak memory 192852 kb
Host smart-f1a86fe8-e82c-4ef5-a1d6-0b7f267b97c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688730176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3688730176
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.533099806
Short name T91
Test name
Test status
Simulation time 133170667267 ps
CPU time 182.19 seconds
Started Aug 14 04:32:13 PM PDT 24
Finished Aug 14 04:35:15 PM PDT 24
Peak memory 192100 kb
Host smart-e3fc57dd-7bb0-4bc2-ab72-d5a6f98a8052
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533099806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.533099806
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.4115529707
Short name T100
Test name
Test status
Simulation time 271328983158 ps
CPU time 96.16 seconds
Started Aug 14 04:32:17 PM PDT 24
Finished Aug 14 04:33:53 PM PDT 24
Peak memory 193156 kb
Host smart-3d05abf7-f43f-4c02-ad7f-610cbdbc072c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115529707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.4115529707
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.788246486
Short name T145
Test name
Test status
Simulation time 11637618159 ps
CPU time 24.46 seconds
Started Aug 14 04:32:23 PM PDT 24
Finished Aug 14 04:32:48 PM PDT 24
Peak memory 206860 kb
Host smart-c024b115-cd70-48d6-8ea5-f366d61dad2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788246486 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.788246486
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1564332753
Short name T122
Test name
Test status
Simulation time 452940544519 ps
CPU time 596.29 seconds
Started Aug 14 04:32:21 PM PDT 24
Finished Aug 14 04:42:17 PM PDT 24
Peak memory 192640 kb
Host smart-71a02d14-152f-4ab4-b395-e2c0a7deb2ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564332753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1564332753
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3224921389
Short name T77
Test name
Test status
Simulation time 5815786934 ps
CPU time 18.69 seconds
Started Aug 14 04:31:45 PM PDT 24
Finished Aug 14 04:32:03 PM PDT 24
Peak memory 206976 kb
Host smart-1184a2bc-5171-4189-b904-a55e4a1e325e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224921389 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3224921389
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1143310079
Short name T18
Test name
Test status
Simulation time 26694309381 ps
CPU time 11.74 seconds
Started Aug 14 04:31:49 PM PDT 24
Finished Aug 14 04:32:00 PM PDT 24
Peak memory 198428 kb
Host smart-f505848c-bad5-489d-bc9f-f3ba0a6dfbab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143310079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1143310079
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1203065724
Short name T140
Test name
Test status
Simulation time 152463883492 ps
CPU time 245.62 seconds
Started Aug 14 04:31:29 PM PDT 24
Finished Aug 14 04:35:45 PM PDT 24
Peak memory 193020 kb
Host smart-efbf824b-dbf7-470d-8b8f-fbf5d2b22c74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203065724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1203065724
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1372423401
Short name T101
Test name
Test status
Simulation time 33701093569 ps
CPU time 34.68 seconds
Started Aug 14 04:31:51 PM PDT 24
Finished Aug 14 04:32:26 PM PDT 24
Peak memory 198668 kb
Host smart-30fefc9a-de4f-4383-9cd7-dddbd32e7573
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372423401 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1372423401
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3135817627
Short name T1
Test name
Test status
Simulation time 12225750481 ps
CPU time 24.99 seconds
Started Aug 14 04:31:39 PM PDT 24
Finished Aug 14 04:32:04 PM PDT 24
Peak memory 206884 kb
Host smart-073c172d-8af6-44ce-bf74-d574a32435e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135817627 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3135817627
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1164056217
Short name T19
Test name
Test status
Simulation time 190944510441 ps
CPU time 140.93 seconds
Started Aug 14 04:31:42 PM PDT 24
Finished Aug 14 04:34:03 PM PDT 24
Peak memory 198372 kb
Host smart-5ef85852-d32a-46ca-bde1-32e88584384b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164056217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1164056217
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.98778336
Short name T139
Test name
Test status
Simulation time 128352513349 ps
CPU time 52.55 seconds
Started Aug 14 04:31:53 PM PDT 24
Finished Aug 14 04:32:45 PM PDT 24
Peak memory 198408 kb
Host smart-6145fd43-f8d2-4874-b278-9c8c6b8b81cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98778336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_al
l.98778336
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2816146874
Short name T135
Test name
Test status
Simulation time 100614150177 ps
CPU time 82.85 seconds
Started Aug 14 04:31:38 PM PDT 24
Finished Aug 14 04:33:01 PM PDT 24
Peak memory 198444 kb
Host smart-a8897a8e-91df-4714-b897-1f26fb04941f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816146874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2816146874
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3072556914
Short name T26
Test name
Test status
Simulation time 3844773921 ps
CPU time 22.24 seconds
Started Aug 14 04:31:39 PM PDT 24
Finished Aug 14 04:32:01 PM PDT 24
Peak memory 199064 kb
Host smart-256c1ab2-06a7-4374-8f63-f088b25fcab9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072556914 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3072556914
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.319780017
Short name T131
Test name
Test status
Simulation time 582630591 ps
CPU time 0.75 seconds
Started Aug 14 04:31:39 PM PDT 24
Finished Aug 14 04:31:40 PM PDT 24
Peak memory 196836 kb
Host smart-9badd62b-125b-41b3-b091-cf216cc2402c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319780017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.319780017
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3478720244
Short name T134
Test name
Test status
Simulation time 44834701632 ps
CPU time 30.14 seconds
Started Aug 14 04:31:57 PM PDT 24
Finished Aug 14 04:32:27 PM PDT 24
Peak memory 192068 kb
Host smart-db76f8ac-3a30-4955-8bfb-b9a134314ccb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478720244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3478720244
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2795109560
Short name T138
Test name
Test status
Simulation time 6529489316 ps
CPU time 33.33 seconds
Started Aug 14 04:32:03 PM PDT 24
Finished Aug 14 04:32:36 PM PDT 24
Peak memory 198712 kb
Host smart-66d9251e-ea3e-456a-a207-5f5fcfc5f64d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795109560 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2795109560
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1833557374
Short name T93
Test name
Test status
Simulation time 151209085146 ps
CPU time 51.79 seconds
Started Aug 14 04:32:17 PM PDT 24
Finished Aug 14 04:33:09 PM PDT 24
Peak memory 193180 kb
Host smart-f485158a-1432-495a-b12b-b8bb5f806cd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833557374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1833557374
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2013482713
Short name T82
Test name
Test status
Simulation time 3976102251 ps
CPU time 11.78 seconds
Started Aug 14 04:32:17 PM PDT 24
Finished Aug 14 04:32:29 PM PDT 24
Peak memory 198728 kb
Host smart-a6476f05-2838-4f7c-8419-5d8e180136e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013482713 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2013482713
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.782519902
Short name T126
Test name
Test status
Simulation time 207479917047 ps
CPU time 294.71 seconds
Started Aug 14 04:32:16 PM PDT 24
Finished Aug 14 04:37:10 PM PDT 24
Peak memory 192064 kb
Host smart-bfe53ebe-6b83-463f-b842-c6a83824de0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782519902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.782519902
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2244018046
Short name T115
Test name
Test status
Simulation time 187376442665 ps
CPU time 297.96 seconds
Started Aug 14 04:32:28 PM PDT 24
Finished Aug 14 04:37:26 PM PDT 24
Peak memory 198408 kb
Host smart-5b5dc194-d00b-43ad-950c-5b4df89c0fbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244018046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2244018046
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.4082718656
Short name T87
Test name
Test status
Simulation time 531480410 ps
CPU time 0.75 seconds
Started Aug 14 04:32:24 PM PDT 24
Finished Aug 14 04:32:25 PM PDT 24
Peak memory 196864 kb
Host smart-fced8826-5e22-49c1-9a62-36bdc196f3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082718656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.4082718656
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2087003704
Short name T109
Test name
Test status
Simulation time 4518091821 ps
CPU time 28.32 seconds
Started Aug 14 04:32:09 PM PDT 24
Finished Aug 14 04:32:37 PM PDT 24
Peak memory 206916 kb
Host smart-7a427de4-9b23-45c9-9db9-515ea3a638e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087003704 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2087003704
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2710642226
Short name T133
Test name
Test status
Simulation time 374375253 ps
CPU time 1.16 seconds
Started Aug 14 04:31:36 PM PDT 24
Finished Aug 14 04:31:38 PM PDT 24
Peak memory 196852 kb
Host smart-692c85db-df73-41ac-ac20-79b711ed0052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710642226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2710642226
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1863318480
Short name T45
Test name
Test status
Simulation time 571436548 ps
CPU time 1.32 seconds
Started Aug 14 04:31:40 PM PDT 24
Finished Aug 14 04:31:42 PM PDT 24
Peak memory 196792 kb
Host smart-fdc09d2b-6ab8-4cab-aa9f-81ed783a5161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863318480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1863318480
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.2033149640
Short name T130
Test name
Test status
Simulation time 72167422058 ps
CPU time 115.66 seconds
Started Aug 14 04:31:22 PM PDT 24
Finished Aug 14 04:33:18 PM PDT 24
Peak memory 192056 kb
Host smart-a4fa2567-e215-4064-82ea-5e0dfc8b14ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033149640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.2033149640
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3455779657
Short name T127
Test name
Test status
Simulation time 4495229698 ps
CPU time 39.6 seconds
Started Aug 14 04:31:59 PM PDT 24
Finished Aug 14 04:32:38 PM PDT 24
Peak memory 215116 kb
Host smart-1485dc2d-23fc-4222-9e1b-d6a11be8f1ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455779657 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3455779657
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.336688687
Short name T128
Test name
Test status
Simulation time 603432621 ps
CPU time 0.68 seconds
Started Aug 14 04:32:14 PM PDT 24
Finished Aug 14 04:32:15 PM PDT 24
Peak memory 196856 kb
Host smart-5040b83f-761c-4f03-80ef-fe21fee517b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336688687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.336688687
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.812799615
Short name T125
Test name
Test status
Simulation time 482472864 ps
CPU time 0.83 seconds
Started Aug 14 04:32:20 PM PDT 24
Finished Aug 14 04:32:21 PM PDT 24
Peak memory 196992 kb
Host smart-8403d375-2b2c-4cbf-89f5-2814d527691d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812799615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.812799615
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.512822899
Short name T119
Test name
Test status
Simulation time 584272392 ps
CPU time 1.34 seconds
Started Aug 14 04:32:26 PM PDT 24
Finished Aug 14 04:32:28 PM PDT 24
Peak memory 196820 kb
Host smart-f43211e4-a802-400a-9474-214ebcdef59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512822899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.512822899
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3833553100
Short name T80
Test name
Test status
Simulation time 162474077886 ps
CPU time 50.06 seconds
Started Aug 14 04:31:40 PM PDT 24
Finished Aug 14 04:32:30 PM PDT 24
Peak memory 192028 kb
Host smart-cfb37f92-e0bb-4741-bf93-fb6e908940a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833553100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3833553100
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1735229707
Short name T113
Test name
Test status
Simulation time 470025762 ps
CPU time 0.7 seconds
Started Aug 14 04:31:36 PM PDT 24
Finished Aug 14 04:31:37 PM PDT 24
Peak memory 196748 kb
Host smart-a7e306b6-a5f5-4cab-b356-0c5892eb7d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735229707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1735229707
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.4033508543
Short name T118
Test name
Test status
Simulation time 518188115 ps
CPU time 0.74 seconds
Started Aug 14 04:31:38 PM PDT 24
Finished Aug 14 04:31:39 PM PDT 24
Peak memory 196784 kb
Host smart-0887e0ec-541e-4383-baee-d53ca3c0ad1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033508543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.4033508543
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3678254040
Short name T73
Test name
Test status
Simulation time 2519233571 ps
CPU time 13.92 seconds
Started Aug 14 04:31:36 PM PDT 24
Finished Aug 14 04:31:50 PM PDT 24
Peak memory 198792 kb
Host smart-dd63a648-bdf6-4eaa-8666-63b5d21d78b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678254040 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3678254040
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2182816261
Short name T106
Test name
Test status
Simulation time 561796047 ps
CPU time 0.67 seconds
Started Aug 14 04:32:06 PM PDT 24
Finished Aug 14 04:32:07 PM PDT 24
Peak memory 196980 kb
Host smart-a6029234-3ecc-4131-adc8-b07c2d56e6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182816261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2182816261
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1884689871
Short name T117
Test name
Test status
Simulation time 537274289 ps
CPU time 0.98 seconds
Started Aug 14 04:31:52 PM PDT 24
Finished Aug 14 04:31:53 PM PDT 24
Peak memory 196784 kb
Host smart-ba871d12-4b6b-46ae-bf3c-f5f4d8e07b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884689871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1884689871
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.3952389529
Short name T124
Test name
Test status
Simulation time 583752696 ps
CPU time 0.66 seconds
Started Aug 14 04:32:17 PM PDT 24
Finished Aug 14 04:32:18 PM PDT 24
Peak memory 196980 kb
Host smart-60af7ff5-3918-44ea-ab3f-46fe8de54340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952389529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3952389529
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2351516247
Short name T96
Test name
Test status
Simulation time 558512456 ps
CPU time 0.93 seconds
Started Aug 14 04:32:16 PM PDT 24
Finished Aug 14 04:32:17 PM PDT 24
Peak memory 196820 kb
Host smart-5a0d8a05-d918-4943-9be1-bd90f7d80b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351516247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2351516247
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2035550554
Short name T28
Test name
Test status
Simulation time 228037062106 ps
CPU time 85.95 seconds
Started Aug 14 04:31:28 PM PDT 24
Finished Aug 14 04:32:54 PM PDT 24
Peak memory 192088 kb
Host smart-3277f849-92a4-484f-bc69-d6c09d4a6c30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035550554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2035550554
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2281033010
Short name T157
Test name
Test status
Simulation time 2996406624 ps
CPU time 23.9 seconds
Started Aug 14 04:31:28 PM PDT 24
Finished Aug 14 04:31:52 PM PDT 24
Peak memory 198672 kb
Host smart-b4254475-a4bc-4cd7-9c6f-81b9b0135150
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281033010 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2281033010
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1270966373
Short name T27
Test name
Test status
Simulation time 455925867 ps
CPU time 0.7 seconds
Started Aug 14 04:32:00 PM PDT 24
Finished Aug 14 04:32:00 PM PDT 24
Peak memory 196832 kb
Host smart-a194a1a0-3398-42fa-a9f6-20da0d0f985f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270966373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1270966373
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3205726537
Short name T88
Test name
Test status
Simulation time 561620093 ps
CPU time 0.9 seconds
Started Aug 14 04:32:09 PM PDT 24
Finished Aug 14 04:32:10 PM PDT 24
Peak memory 196888 kb
Host smart-2757ea01-e80a-4c1c-9d6d-5b4b37dc6433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205726537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3205726537
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1363567420
Short name T30
Test name
Test status
Simulation time 489130792 ps
CPU time 0.88 seconds
Started Aug 14 04:32:01 PM PDT 24
Finished Aug 14 04:32:02 PM PDT 24
Peak memory 196980 kb
Host smart-d6614658-7c4f-4be5-a9f0-95edaaeb2c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363567420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1363567420
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3236315375
Short name T4
Test name
Test status
Simulation time 506759823 ps
CPU time 0.81 seconds
Started Aug 14 04:32:05 PM PDT 24
Finished Aug 14 04:32:06 PM PDT 24
Peak memory 196816 kb
Host smart-83f10292-73c6-4a49-b942-8d500caab1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236315375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3236315375
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1026811599
Short name T99
Test name
Test status
Simulation time 175232077352 ps
CPU time 249.7 seconds
Started Aug 14 04:32:13 PM PDT 24
Finished Aug 14 04:36:23 PM PDT 24
Peak memory 192616 kb
Host smart-b44bdd3f-507a-4b43-8c38-13f732fd1ae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026811599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1026811599
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.141881328
Short name T5
Test name
Test status
Simulation time 446806149 ps
CPU time 0.74 seconds
Started Aug 14 04:31:41 PM PDT 24
Finished Aug 14 04:31:42 PM PDT 24
Peak memory 196860 kb
Host smart-c9800592-965f-4c31-a061-280b80a9713a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141881328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.141881328
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3405403716
Short name T10
Test name
Test status
Simulation time 599182497 ps
CPU time 0.69 seconds
Started Aug 14 04:31:28 PM PDT 24
Finished Aug 14 04:31:29 PM PDT 24
Peak memory 196820 kb
Host smart-ac1bd4d1-75df-4700-af92-786764e035d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405403716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3405403716
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3271772478
Short name T107
Test name
Test status
Simulation time 537759939 ps
CPU time 1.4 seconds
Started Aug 14 04:31:44 PM PDT 24
Finished Aug 14 04:31:46 PM PDT 24
Peak memory 196904 kb
Host smart-9b3e3de7-f3e3-4bd6-b84c-67434973e7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271772478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3271772478
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1225158986
Short name T75
Test name
Test status
Simulation time 5465616574 ps
CPU time 34.82 seconds
Started Aug 14 04:31:45 PM PDT 24
Finished Aug 14 04:32:19 PM PDT 24
Peak memory 215100 kb
Host smart-f2cc175e-1083-4e78-9d67-92ef66ea7ea3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225158986 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1225158986
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2419345815
Short name T152
Test name
Test status
Simulation time 196093210674 ps
CPU time 273.52 seconds
Started Aug 14 04:32:17 PM PDT 24
Finished Aug 14 04:36:50 PM PDT 24
Peak memory 192060 kb
Host smart-6214091e-2c3c-42c8-92cd-5e1dc1cdeb32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419345815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2419345815
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3579119166
Short name T160
Test name
Test status
Simulation time 193321221418 ps
CPU time 272.18 seconds
Started Aug 14 04:32:22 PM PDT 24
Finished Aug 14 04:36:55 PM PDT 24
Peak memory 197300 kb
Host smart-a9f076eb-6376-4b54-83b6-1368090b81ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579119166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3579119166
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1950334934
Short name T148
Test name
Test status
Simulation time 2358870509 ps
CPU time 17.2 seconds
Started Aug 14 04:32:17 PM PDT 24
Finished Aug 14 04:32:34 PM PDT 24
Peak memory 206904 kb
Host smart-cb6e5b34-b7a2-428e-9934-e18a66573ff1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950334934 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1950334934
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2488090086
Short name T166
Test name
Test status
Simulation time 299963541620 ps
CPU time 35.67 seconds
Started Aug 14 04:31:50 PM PDT 24
Finished Aug 14 04:32:26 PM PDT 24
Peak memory 192080 kb
Host smart-8cb3d366-6d31-4ced-9499-a72aa7e526f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488090086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2488090086
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.800430789
Short name T144
Test name
Test status
Simulation time 376726081669 ps
CPU time 254.09 seconds
Started Aug 14 04:32:08 PM PDT 24
Finished Aug 14 04:36:22 PM PDT 24
Peak memory 198416 kb
Host smart-b176cad6-7023-4fe1-a468-1ed7bcddcf99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800430789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.800430789
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1656525282
Short name T179
Test name
Test status
Simulation time 493726150 ps
CPU time 1.19 seconds
Started Aug 14 04:31:56 PM PDT 24
Finished Aug 14 04:31:57 PM PDT 24
Peak memory 196752 kb
Host smart-b56be900-6514-4076-80ed-957f23c27392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656525282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1656525282
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1787819707
Short name T111
Test name
Test status
Simulation time 519746758 ps
CPU time 1.22 seconds
Started Aug 14 04:31:52 PM PDT 24
Finished Aug 14 04:31:54 PM PDT 24
Peak memory 196880 kb
Host smart-dd579e0c-93d5-4cd6-bfdb-57385b2157a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787819707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1787819707
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.4225617627
Short name T167
Test name
Test status
Simulation time 429457599 ps
CPU time 0.63 seconds
Started Aug 14 04:32:12 PM PDT 24
Finished Aug 14 04:32:13 PM PDT 24
Peak memory 196724 kb
Host smart-f2917f3a-8a99-48da-9bfb-ab4c34f0da2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225617627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.4225617627
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3823477340
Short name T161
Test name
Test status
Simulation time 604687086 ps
CPU time 0.78 seconds
Started Aug 14 04:32:25 PM PDT 24
Finished Aug 14 04:32:26 PM PDT 24
Peak memory 196864 kb
Host smart-0328e829-8461-43b5-825e-99572c8541d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823477340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3823477340
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.897767589
Short name T187
Test name
Test status
Simulation time 7743584605 ps
CPU time 3.81 seconds
Started Aug 14 04:28:19 PM PDT 24
Finished Aug 14 04:28:23 PM PDT 24
Peak memory 198196 kb
Host smart-2eff06db-3cf6-4208-a165-92b4da80514b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897767589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.897767589
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2719969334
Short name T175
Test name
Test status
Simulation time 550788244 ps
CPU time 1.33 seconds
Started Aug 14 04:31:18 PM PDT 24
Finished Aug 14 04:31:20 PM PDT 24
Peak memory 196792 kb
Host smart-d4ca4f2f-3b25-47f7-98e1-acfa3436ec28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719969334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2719969334
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1256023187
Short name T173
Test name
Test status
Simulation time 542342204 ps
CPU time 1.37 seconds
Started Aug 14 04:31:42 PM PDT 24
Finished Aug 14 04:31:43 PM PDT 24
Peak memory 196780 kb
Host smart-b550c801-910a-4616-bd74-a3b1098a8ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256023187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1256023187
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3463090410
Short name T121
Test name
Test status
Simulation time 413150340 ps
CPU time 0.74 seconds
Started Aug 14 04:31:25 PM PDT 24
Finished Aug 14 04:31:26 PM PDT 24
Peak memory 196812 kb
Host smart-9d743c54-3daa-447e-8445-76847ef79edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463090410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3463090410
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.785186417
Short name T168
Test name
Test status
Simulation time 476640240 ps
CPU time 1.27 seconds
Started Aug 14 04:31:35 PM PDT 24
Finished Aug 14 04:31:36 PM PDT 24
Peak memory 196812 kb
Host smart-22a4e28e-8ebb-43bb-ad6f-2a8f1ede2b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785186417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.785186417
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1734267995
Short name T13
Test name
Test status
Simulation time 532835516 ps
CPU time 0.78 seconds
Started Aug 14 04:31:56 PM PDT 24
Finished Aug 14 04:31:57 PM PDT 24
Peak memory 196884 kb
Host smart-7da3773d-c223-4246-b4c7-9c66e7eac4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734267995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1734267995
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.3603445046
Short name T172
Test name
Test status
Simulation time 492218472 ps
CPU time 0.76 seconds
Started Aug 14 04:31:44 PM PDT 24
Finished Aug 14 04:31:45 PM PDT 24
Peak memory 196884 kb
Host smart-4ac10d0e-a91b-49f4-bd98-49c1dfe0bf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603445046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3603445046
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2094651685
Short name T178
Test name
Test status
Simulation time 102136349298 ps
CPU time 151.13 seconds
Started Aug 14 04:32:09 PM PDT 24
Finished Aug 14 04:34:50 PM PDT 24
Peak memory 193188 kb
Host smart-dbf3c54f-e09a-4e39-aba2-062bd85e96c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094651685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2094651685
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1177575668
Short name T164
Test name
Test status
Simulation time 565153725 ps
CPU time 1.51 seconds
Started Aug 14 04:32:01 PM PDT 24
Finished Aug 14 04:32:08 PM PDT 24
Peak memory 196748 kb
Host smart-78a20b99-da15-4c56-92ed-b76d2ae2c2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177575668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1177575668
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3989272697
Short name T154
Test name
Test status
Simulation time 412166302 ps
CPU time 0.73 seconds
Started Aug 14 04:32:04 PM PDT 24
Finished Aug 14 04:32:05 PM PDT 24
Peak memory 196780 kb
Host smart-71875c44-3728-43f2-b559-4467b66c8e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989272697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3989272697
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3037075230
Short name T169
Test name
Test status
Simulation time 2676362893 ps
CPU time 22.96 seconds
Started Aug 14 04:31:58 PM PDT 24
Finished Aug 14 04:32:21 PM PDT 24
Peak memory 199132 kb
Host smart-c5367a8f-f1fc-4202-bbe1-4a7fd89ddd0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037075230 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3037075230
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2846513092
Short name T155
Test name
Test status
Simulation time 504875097 ps
CPU time 0.79 seconds
Started Aug 14 04:31:31 PM PDT 24
Finished Aug 14 04:31:32 PM PDT 24
Peak memory 196900 kb
Host smart-4d4aa417-85fb-4a30-9403-18cc26e18b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846513092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2846513092
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3809473598
Short name T132
Test name
Test status
Simulation time 526299207 ps
CPU time 1.4 seconds
Started Aug 14 04:32:27 PM PDT 24
Finished Aug 14 04:32:29 PM PDT 24
Peak memory 196744 kb
Host smart-3f385070-d037-4c97-acf4-ee7aefd5df6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809473598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3809473598
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3163657743
Short name T23
Test name
Test status
Simulation time 3182701062 ps
CPU time 25.31 seconds
Started Aug 14 04:31:44 PM PDT 24
Finished Aug 14 04:32:09 PM PDT 24
Peak memory 206872 kb
Host smart-2f04c127-8c71-4e47-b4db-39d9fcfe5f9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163657743 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3163657743
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.33167917
Short name T174
Test name
Test status
Simulation time 516576883 ps
CPU time 0.92 seconds
Started Aug 14 04:32:00 PM PDT 24
Finished Aug 14 04:32:01 PM PDT 24
Peak memory 196876 kb
Host smart-aad4087a-174c-4ae8-afc4-0a6087f05fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33167917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.33167917
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1878793306
Short name T171
Test name
Test status
Simulation time 432117764 ps
CPU time 1.25 seconds
Started Aug 14 04:31:37 PM PDT 24
Finished Aug 14 04:31:38 PM PDT 24
Peak memory 196796 kb
Host smart-2ec0f966-4241-4d06-8dd7-4ff4e9b1bf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878793306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1878793306
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.522678383
Short name T8
Test name
Test status
Simulation time 416689773 ps
CPU time 0.62 seconds
Started Aug 14 04:31:31 PM PDT 24
Finished Aug 14 04:31:31 PM PDT 24
Peak memory 196804 kb
Host smart-d19ddfc9-e898-4b12-ba58-2b1f109e224d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522678383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.522678383
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1948227428
Short name T158
Test name
Test status
Simulation time 427962965 ps
CPU time 0.89 seconds
Started Aug 14 04:31:29 PM PDT 24
Finished Aug 14 04:31:30 PM PDT 24
Peak memory 196788 kb
Host smart-bfc09884-f1b8-411a-a706-f8941f77eb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948227428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1948227428
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2147635090
Short name T180
Test name
Test status
Simulation time 443168887 ps
CPU time 0.92 seconds
Started Aug 14 04:31:23 PM PDT 24
Finished Aug 14 04:31:24 PM PDT 24
Peak memory 196780 kb
Host smart-ec5cba27-091e-4e20-beda-78b3f342c495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147635090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2147635090
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.92246513
Short name T162
Test name
Test status
Simulation time 509771599 ps
CPU time 0.69 seconds
Started Aug 14 04:31:54 PM PDT 24
Finished Aug 14 04:31:55 PM PDT 24
Peak memory 196880 kb
Host smart-9732ea95-c7f4-4a88-96cb-646b9edd6f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92246513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.92246513
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1760741719
Short name T159
Test name
Test status
Simulation time 513726737 ps
CPU time 1.38 seconds
Started Aug 14 04:31:57 PM PDT 24
Finished Aug 14 04:31:58 PM PDT 24
Peak memory 196928 kb
Host smart-ac3bb3c3-de76-40f6-a392-1df324dad705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760741719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1760741719
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3237824713
Short name T181
Test name
Test status
Simulation time 386830322 ps
CPU time 0.83 seconds
Started Aug 14 04:31:56 PM PDT 24
Finished Aug 14 04:31:57 PM PDT 24
Peak memory 196796 kb
Host smart-ca3c1055-a90d-45ce-9c9c-f5b7067f25db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237824713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3237824713
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.753425653
Short name T163
Test name
Test status
Simulation time 484650965 ps
CPU time 1.25 seconds
Started Aug 14 04:31:43 PM PDT 24
Finished Aug 14 04:31:45 PM PDT 24
Peak memory 196816 kb
Host smart-ba61364a-4545-4aee-932e-ac7f1b74c233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753425653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.753425653
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1271370643
Short name T156
Test name
Test status
Simulation time 401138142 ps
CPU time 1.13 seconds
Started Aug 14 04:32:09 PM PDT 24
Finished Aug 14 04:32:10 PM PDT 24
Peak memory 196856 kb
Host smart-068fca8f-1a2f-431f-81c7-1ae1fb3e6f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271370643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1271370643
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.392220898
Short name T176
Test name
Test status
Simulation time 426324091 ps
CPU time 1.09 seconds
Started Aug 14 04:32:13 PM PDT 24
Finished Aug 14 04:32:14 PM PDT 24
Peak memory 196784 kb
Host smart-2c986dd4-7814-4e09-b6a1-649f708542a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392220898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.392220898
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.779957560
Short name T25
Test name
Test status
Simulation time 340943037 ps
CPU time 1.09 seconds
Started Aug 14 04:32:15 PM PDT 24
Finished Aug 14 04:32:16 PM PDT 24
Peak memory 196784 kb
Host smart-e0ff6abc-3a3f-454b-a149-3e49d9efa9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779957560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.779957560
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1902483927
Short name T170
Test name
Test status
Simulation time 7318115434 ps
CPU time 33.24 seconds
Started Aug 14 04:32:31 PM PDT 24
Finished Aug 14 04:33:04 PM PDT 24
Peak memory 214604 kb
Host smart-e90e4ce9-ed92-4aa9-8eba-0c077b982364
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902483927 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1902483927
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.174071827
Short name T165
Test name
Test status
Simulation time 355627827 ps
CPU time 1.13 seconds
Started Aug 14 04:32:21 PM PDT 24
Finished Aug 14 04:32:22 PM PDT 24
Peak memory 196796 kb
Host smart-342b3c69-fb4e-4c20-977e-bdea7e66b37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174071827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.174071827
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1760917785
Short name T177
Test name
Test status
Simulation time 433345913 ps
CPU time 1.24 seconds
Started Aug 14 04:32:19 PM PDT 24
Finished Aug 14 04:32:20 PM PDT 24
Peak memory 196840 kb
Host smart-9fd87761-bc76-40e4-a1d2-434c48240447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760917785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1760917785
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2152721470
Short name T108
Test name
Test status
Simulation time 390996879 ps
CPU time 1.13 seconds
Started Aug 14 04:32:05 PM PDT 24
Finished Aug 14 04:32:06 PM PDT 24
Peak memory 196808 kb
Host smart-b46eb435-0e52-40d3-b100-42e8ef4633cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152721470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2152721470
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.11686025
Short name T183
Test name
Test status
Simulation time 534697211 ps
CPU time 1.35 seconds
Started Aug 14 04:31:27 PM PDT 24
Finished Aug 14 04:31:28 PM PDT 24
Peak memory 196780 kb
Host smart-29fb8969-16de-4fd8-a257-f080356c8fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11686025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.11686025
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1659019456
Short name T52
Test name
Test status
Simulation time 982693774 ps
CPU time 2.34 seconds
Started Aug 14 04:28:30 PM PDT 24
Finished Aug 14 04:28:33 PM PDT 24
Peak memory 192116 kb
Host smart-b3782b3b-2a9c-4571-86f8-5b8a233d0498
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659019456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1659019456
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3788424465
Short name T70
Test name
Test status
Simulation time 752895409 ps
CPU time 1.2 seconds
Started Aug 14 04:28:10 PM PDT 24
Finished Aug 14 04:28:11 PM PDT 24
Peak memory 192900 kb
Host smart-a5c00387-2944-4bb3-921c-7d66e400fa4a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788424465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3788424465
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3013256931
Short name T348
Test name
Test status
Simulation time 412598109 ps
CPU time 0.77 seconds
Started Aug 14 04:28:20 PM PDT 24
Finished Aug 14 04:28:21 PM PDT 24
Peak memory 196040 kb
Host smart-f34f86df-6326-4df7-888b-72a6d9b5828b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013256931 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3013256931
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3446260528
Short name T368
Test name
Test status
Simulation time 307453774 ps
CPU time 1.05 seconds
Started Aug 14 04:28:10 PM PDT 24
Finished Aug 14 04:28:11 PM PDT 24
Peak memory 191972 kb
Host smart-ad915cb1-29cd-4a7d-ae44-fbd1c2d92d86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446260528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3446260528
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2857767534
Short name T363
Test name
Test status
Simulation time 495005275 ps
CPU time 1.49 seconds
Started Aug 14 04:28:12 PM PDT 24
Finished Aug 14 04:28:14 PM PDT 24
Peak memory 183656 kb
Host smart-c796ef14-be25-4ba4-a142-9738d60c8e7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857767534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2857767534
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3955600379
Short name T380
Test name
Test status
Simulation time 309868006 ps
CPU time 0.89 seconds
Started Aug 14 04:27:45 PM PDT 24
Finished Aug 14 04:27:46 PM PDT 24
Peak memory 183576 kb
Host smart-6d0917e8-3d18-4faf-a409-7cb60f89e682
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955600379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3955600379
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2183466792
Short name T339
Test name
Test status
Simulation time 503400545 ps
CPU time 1.27 seconds
Started Aug 14 04:28:09 PM PDT 24
Finished Aug 14 04:28:10 PM PDT 24
Peak memory 183576 kb
Host smart-8f25a1b4-6749-42a4-a0f5-99d1acb85a28
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183466792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2183466792
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3807842729
Short name T332
Test name
Test status
Simulation time 1258156342 ps
CPU time 2.81 seconds
Started Aug 14 04:27:52 PM PDT 24
Finished Aug 14 04:27:55 PM PDT 24
Peak memory 192900 kb
Host smart-18d08b13-b2dd-49f8-b9fb-44745cddc038
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807842729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3807842729
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3872018058
Short name T290
Test name
Test status
Simulation time 484224672 ps
CPU time 1.93 seconds
Started Aug 14 04:27:42 PM PDT 24
Finished Aug 14 04:27:44 PM PDT 24
Peak memory 198524 kb
Host smart-f3c9a461-2ae8-417d-90ee-cf2aa975a881
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872018058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3872018058
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2041562612
Short name T184
Test name
Test status
Simulation time 4565379491 ps
CPU time 1.74 seconds
Started Aug 14 04:28:19 PM PDT 24
Finished Aug 14 04:28:21 PM PDT 24
Peak memory 197508 kb
Host smart-e0055175-f244-4fc8-af33-b2a94c1c0f8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041562612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2041562612
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3062397258
Short name T71
Test name
Test status
Simulation time 592206582 ps
CPU time 1.67 seconds
Started Aug 14 04:28:11 PM PDT 24
Finished Aug 14 04:28:13 PM PDT 24
Peak memory 193244 kb
Host smart-e92aef41-6e87-4d1d-88a0-d7324458c9b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062397258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3062397258
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4209889958
Short name T48
Test name
Test status
Simulation time 4012873111 ps
CPU time 6.14 seconds
Started Aug 14 04:28:14 PM PDT 24
Finished Aug 14 04:28:20 PM PDT 24
Peak memory 195896 kb
Host smart-d211181f-d314-4006-a60d-7939c2765022
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209889958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.4209889958
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1602681357
Short name T362
Test name
Test status
Simulation time 868822046 ps
CPU time 0.9 seconds
Started Aug 14 04:28:17 PM PDT 24
Finished Aug 14 04:28:18 PM PDT 24
Peak memory 192104 kb
Host smart-6a3f45be-00df-4bbb-bd3d-602e74a344fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602681357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1602681357
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2953122422
Short name T395
Test name
Test status
Simulation time 561621636 ps
CPU time 0.86 seconds
Started Aug 14 04:28:14 PM PDT 24
Finished Aug 14 04:28:15 PM PDT 24
Peak memory 196348 kb
Host smart-42922cf9-1eb6-424c-bfa4-70eab64b47b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953122422 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2953122422
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2260596370
Short name T355
Test name
Test status
Simulation time 520166340 ps
CPU time 0.93 seconds
Started Aug 14 04:27:59 PM PDT 24
Finished Aug 14 04:28:00 PM PDT 24
Peak memory 191988 kb
Host smart-b511f56b-2bd2-4fb7-a329-352edeac3122
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260596370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2260596370
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3303171374
Short name T397
Test name
Test status
Simulation time 321202811 ps
CPU time 0.91 seconds
Started Aug 14 04:28:07 PM PDT 24
Finished Aug 14 04:28:08 PM PDT 24
Peak memory 183616 kb
Host smart-42875732-13c6-458b-a401-b254981385fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303171374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3303171374
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3093215440
Short name T418
Test name
Test status
Simulation time 369815007 ps
CPU time 0.64 seconds
Started Aug 14 04:28:10 PM PDT 24
Finished Aug 14 04:28:11 PM PDT 24
Peak memory 183524 kb
Host smart-ecff9251-3a79-48c1-866b-b27a1561eefc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093215440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3093215440
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.614224418
Short name T300
Test name
Test status
Simulation time 500133925 ps
CPU time 0.89 seconds
Started Aug 14 04:28:16 PM PDT 24
Finished Aug 14 04:28:17 PM PDT 24
Peak memory 183560 kb
Host smart-9512e598-c66d-4509-a207-91204d4f0b48
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614224418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.614224418
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1178644667
Short name T309
Test name
Test status
Simulation time 517306124 ps
CPU time 2.15 seconds
Started Aug 14 04:28:14 PM PDT 24
Finished Aug 14 04:28:16 PM PDT 24
Peak memory 198312 kb
Host smart-8361481e-04d1-45de-8b3c-2c4282549cbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178644667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1178644667
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.712140977
Short name T36
Test name
Test status
Simulation time 4978038669 ps
CPU time 3.95 seconds
Started Aug 14 04:28:02 PM PDT 24
Finished Aug 14 04:28:06 PM PDT 24
Peak memory 196480 kb
Host smart-d35333ba-8a03-4de2-8c67-1a4dc7bbb57f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712140977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.712140977
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1823953182
Short name T364
Test name
Test status
Simulation time 493424454 ps
CPU time 1.43 seconds
Started Aug 14 04:28:28 PM PDT 24
Finished Aug 14 04:28:30 PM PDT 24
Peak memory 196032 kb
Host smart-78c3ad4d-a230-4161-b80f-39815ee64424
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823953182 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1823953182
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3031678364
Short name T315
Test name
Test status
Simulation time 476042456 ps
CPU time 0.69 seconds
Started Aug 14 04:28:29 PM PDT 24
Finished Aug 14 04:28:30 PM PDT 24
Peak memory 191988 kb
Host smart-014f3436-4a49-465a-9f9b-a51c76bc247e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031678364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3031678364
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3529339839
Short name T409
Test name
Test status
Simulation time 332719056 ps
CPU time 0.96 seconds
Started Aug 14 04:28:09 PM PDT 24
Finished Aug 14 04:28:10 PM PDT 24
Peak memory 192900 kb
Host smart-7aa718da-3d7d-461c-9c4e-de77d7357f01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529339839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3529339839
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3223586479
Short name T354
Test name
Test status
Simulation time 1485900583 ps
CPU time 1.21 seconds
Started Aug 14 04:28:15 PM PDT 24
Finished Aug 14 04:28:16 PM PDT 24
Peak memory 192980 kb
Host smart-4003257e-7681-4ded-9edc-c30b5ffb441b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223586479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3223586479
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.481172634
Short name T298
Test name
Test status
Simulation time 437415835 ps
CPU time 2 seconds
Started Aug 14 04:28:00 PM PDT 24
Finished Aug 14 04:28:02 PM PDT 24
Peak memory 198456 kb
Host smart-e5063d76-b296-404a-88db-1e8719548e33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481172634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.481172634
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1589761820
Short name T317
Test name
Test status
Simulation time 8454747425 ps
CPU time 3.32 seconds
Started Aug 14 04:28:18 PM PDT 24
Finished Aug 14 04:28:22 PM PDT 24
Peak memory 198144 kb
Host smart-7d8afb28-ce1f-4e72-a11e-691b19648832
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589761820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1589761820
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1735854145
Short name T394
Test name
Test status
Simulation time 561453049 ps
CPU time 1.5 seconds
Started Aug 14 04:28:24 PM PDT 24
Finished Aug 14 04:28:26 PM PDT 24
Peak memory 197144 kb
Host smart-4bc78bea-f8e3-47ff-b1c0-f9954d3d3b78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735854145 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1735854145
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1012945139
Short name T349
Test name
Test status
Simulation time 408666761 ps
CPU time 0.64 seconds
Started Aug 14 04:28:13 PM PDT 24
Finished Aug 14 04:28:14 PM PDT 24
Peak memory 192988 kb
Host smart-fb23bffd-baa7-4350-86c6-e1f96ce24c7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012945139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1012945139
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4225354850
Short name T406
Test name
Test status
Simulation time 283748735 ps
CPU time 0.87 seconds
Started Aug 14 04:28:17 PM PDT 24
Finished Aug 14 04:28:18 PM PDT 24
Peak memory 192876 kb
Host smart-638b0c44-3a76-4456-bf5c-ab150fed4f05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225354850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.4225354850
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1297243394
Short name T366
Test name
Test status
Simulation time 2169786341 ps
CPU time 1.95 seconds
Started Aug 14 04:28:36 PM PDT 24
Finished Aug 14 04:28:38 PM PDT 24
Peak memory 195012 kb
Host smart-603b9157-0b87-428b-9825-0276332d2969
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297243394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1297243394
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.4132755557
Short name T331
Test name
Test status
Simulation time 495340414 ps
CPU time 2.38 seconds
Started Aug 14 04:28:26 PM PDT 24
Finished Aug 14 04:28:28 PM PDT 24
Peak memory 198536 kb
Host smart-34286e7d-51c4-4730-8b84-fe275c8c5394
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132755557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.4132755557
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2613537325
Short name T316
Test name
Test status
Simulation time 4141807449 ps
CPU time 6.39 seconds
Started Aug 14 04:28:33 PM PDT 24
Finished Aug 14 04:28:39 PM PDT 24
Peak memory 197860 kb
Host smart-b2ed4236-5ecc-435e-81ee-2b5b2ec8c916
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613537325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.2613537325
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2365479775
Short name T388
Test name
Test status
Simulation time 383010088 ps
CPU time 1.23 seconds
Started Aug 14 04:28:21 PM PDT 24
Finished Aug 14 04:28:23 PM PDT 24
Peak memory 196544 kb
Host smart-40d7140a-83ea-45eb-bae0-3dd6780d8edb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365479775 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2365479775
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3194071344
Short name T55
Test name
Test status
Simulation time 367071952 ps
CPU time 0.81 seconds
Started Aug 14 04:28:10 PM PDT 24
Finished Aug 14 04:28:11 PM PDT 24
Peak memory 193324 kb
Host smart-51d33ad1-7ae1-4fe5-8bcc-c881f72aff93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194071344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3194071344
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2369536276
Short name T321
Test name
Test status
Simulation time 277920105 ps
CPU time 0.92 seconds
Started Aug 14 04:28:08 PM PDT 24
Finished Aug 14 04:28:09 PM PDT 24
Peak memory 183652 kb
Host smart-dc8b0328-c829-4991-92ee-ee44cbbfd18c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369536276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2369536276
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1943979855
Short name T59
Test name
Test status
Simulation time 2357446686 ps
CPU time 3.43 seconds
Started Aug 14 04:28:27 PM PDT 24
Finished Aug 14 04:28:30 PM PDT 24
Peak memory 195004 kb
Host smart-9d929f0b-7c25-4149-8272-e01b11a58287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943979855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1943979855
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.85470038
Short name T413
Test name
Test status
Simulation time 524836433 ps
CPU time 1.33 seconds
Started Aug 14 04:28:28 PM PDT 24
Finished Aug 14 04:28:29 PM PDT 24
Peak memory 198532 kb
Host smart-1e09db8f-2e15-4e6b-a2a7-fa7abd8ca75e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85470038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.85470038
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.306249227
Short name T301
Test name
Test status
Simulation time 4455782012 ps
CPU time 1.55 seconds
Started Aug 14 04:28:41 PM PDT 24
Finished Aug 14 04:28:42 PM PDT 24
Peak memory 197724 kb
Host smart-1e60035f-0ea7-4043-aeb7-a157981de6bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306249227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.306249227
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.566244502
Short name T326
Test name
Test status
Simulation time 495613812 ps
CPU time 0.94 seconds
Started Aug 14 04:28:29 PM PDT 24
Finished Aug 14 04:28:30 PM PDT 24
Peak memory 198356 kb
Host smart-87f0e893-f06a-486d-ad98-af05ddffc2fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566244502 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.566244502
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3379948191
Short name T47
Test name
Test status
Simulation time 425938841 ps
CPU time 0.85 seconds
Started Aug 14 04:28:19 PM PDT 24
Finished Aug 14 04:28:20 PM PDT 24
Peak memory 193200 kb
Host smart-e72654f1-7b7d-4408-909b-7d4d5064b5e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379948191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3379948191
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.382536576
Short name T401
Test name
Test status
Simulation time 296428378 ps
CPU time 0.74 seconds
Started Aug 14 04:28:33 PM PDT 24
Finished Aug 14 04:28:39 PM PDT 24
Peak memory 192904 kb
Host smart-1d733512-8341-4401-aa76-110cd70e165d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382536576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.382536576
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3421372629
Short name T408
Test name
Test status
Simulation time 2279862141 ps
CPU time 2 seconds
Started Aug 14 04:28:28 PM PDT 24
Finished Aug 14 04:28:30 PM PDT 24
Peak memory 194992 kb
Host smart-75508b44-93c3-4b88-b8d0-e97de4d28d3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421372629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3421372629
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3090523480
Short name T371
Test name
Test status
Simulation time 729080811 ps
CPU time 2 seconds
Started Aug 14 04:28:11 PM PDT 24
Finished Aug 14 04:28:13 PM PDT 24
Peak memory 198524 kb
Host smart-be54b237-244d-4b4d-8083-1a46aab65307
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090523480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3090523480
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1888455845
Short name T347
Test name
Test status
Simulation time 3838687875 ps
CPU time 4.16 seconds
Started Aug 14 04:28:17 PM PDT 24
Finished Aug 14 04:28:21 PM PDT 24
Peak memory 196644 kb
Host smart-2800cbb0-bdd0-4c0a-b912-e709ec69b01c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888455845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1888455845
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1388731048
Short name T294
Test name
Test status
Simulation time 338505461 ps
CPU time 1.05 seconds
Started Aug 14 04:28:32 PM PDT 24
Finished Aug 14 04:28:33 PM PDT 24
Peak memory 195768 kb
Host smart-a593d482-6ed6-4357-9610-6bd777a0b6cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388731048 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1388731048
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.998425875
Short name T374
Test name
Test status
Simulation time 409607863 ps
CPU time 0.84 seconds
Started Aug 14 04:28:19 PM PDT 24
Finished Aug 14 04:28:19 PM PDT 24
Peak memory 192932 kb
Host smart-c3ff5706-f901-4d7f-9127-893aa83c3dad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998425875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.998425875
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3308734972
Short name T308
Test name
Test status
Simulation time 295243827 ps
CPU time 0.6 seconds
Started Aug 14 04:28:13 PM PDT 24
Finished Aug 14 04:28:13 PM PDT 24
Peak memory 183652 kb
Host smart-60d21f49-3072-41fc-91b5-a705a040992a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308734972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3308734972
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.4008698381
Short name T359
Test name
Test status
Simulation time 931847883 ps
CPU time 1.87 seconds
Started Aug 14 04:28:24 PM PDT 24
Finished Aug 14 04:28:26 PM PDT 24
Peak memory 193804 kb
Host smart-61dffd9f-e10e-474f-8697-67580ba9336c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008698381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.4008698381
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3148721856
Short name T417
Test name
Test status
Simulation time 376566168 ps
CPU time 1.59 seconds
Started Aug 14 04:28:18 PM PDT 24
Finished Aug 14 04:28:20 PM PDT 24
Peak memory 198516 kb
Host smart-d4629f0b-bf6f-40d8-b6d1-0e34c0d24087
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148721856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3148721856
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2769529417
Short name T415
Test name
Test status
Simulation time 7686277894 ps
CPU time 4.22 seconds
Started Aug 14 04:28:12 PM PDT 24
Finished Aug 14 04:28:16 PM PDT 24
Peak memory 198248 kb
Host smart-ec3bd2a3-3d18-431c-984b-e7ae9d310e45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769529417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2769529417
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2691224775
Short name T398
Test name
Test status
Simulation time 431694994 ps
CPU time 1.43 seconds
Started Aug 14 04:28:07 PM PDT 24
Finished Aug 14 04:28:09 PM PDT 24
Peak memory 196956 kb
Host smart-d84689b7-3ba7-4c5f-af49-f40f14105bae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691224775 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2691224775
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2484662692
Short name T377
Test name
Test status
Simulation time 379481481 ps
CPU time 1.17 seconds
Started Aug 14 04:28:28 PM PDT 24
Finished Aug 14 04:28:30 PM PDT 24
Peak memory 191980 kb
Host smart-93be987a-b52f-49bf-8aa3-efaf9daf9afe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484662692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2484662692
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3102098129
Short name T313
Test name
Test status
Simulation time 439401512 ps
CPU time 0.91 seconds
Started Aug 14 04:28:00 PM PDT 24
Finished Aug 14 04:28:01 PM PDT 24
Peak memory 183656 kb
Host smart-93a1b1d9-b3ee-4e07-abe8-aa662ae05801
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102098129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3102098129
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3108490212
Short name T68
Test name
Test status
Simulation time 1099359834 ps
CPU time 1.29 seconds
Started Aug 14 04:28:18 PM PDT 24
Finished Aug 14 04:28:19 PM PDT 24
Peak memory 193464 kb
Host smart-ce9fa48f-5c52-4d8b-86ef-9bface06d22a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108490212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3108490212
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1429458843
Short name T390
Test name
Test status
Simulation time 435257881 ps
CPU time 1.79 seconds
Started Aug 14 04:28:22 PM PDT 24
Finished Aug 14 04:28:24 PM PDT 24
Peak memory 198268 kb
Host smart-00f503b6-4c56-45ae-8be5-3533bb65433e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429458843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1429458843
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4012844690
Short name T411
Test name
Test status
Simulation time 4173692119 ps
CPU time 2.38 seconds
Started Aug 14 04:28:22 PM PDT 24
Finished Aug 14 04:28:25 PM PDT 24
Peak memory 197876 kb
Host smart-fd497e6a-eb53-4509-af76-530e2c846722
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012844690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.4012844690
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3745924156
Short name T378
Test name
Test status
Simulation time 480645494 ps
CPU time 1.3 seconds
Started Aug 14 04:28:12 PM PDT 24
Finished Aug 14 04:28:13 PM PDT 24
Peak memory 198368 kb
Host smart-649f9686-f2ae-4f60-b79a-781d87f57c65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745924156 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3745924156
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.4241535073
Short name T57
Test name
Test status
Simulation time 394186706 ps
CPU time 1.23 seconds
Started Aug 14 04:28:24 PM PDT 24
Finished Aug 14 04:28:26 PM PDT 24
Peak memory 192948 kb
Host smart-b1f37f9f-0fc8-40bb-8017-82b510267b37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241535073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.4241535073
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2450346731
Short name T289
Test name
Test status
Simulation time 284640507 ps
CPU time 0.59 seconds
Started Aug 14 04:28:25 PM PDT 24
Finished Aug 14 04:28:26 PM PDT 24
Peak memory 183684 kb
Host smart-6e6f5c84-5c29-44da-94ee-4075810346a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450346731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2450346731
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2084748747
Short name T64
Test name
Test status
Simulation time 1410457969 ps
CPU time 3.79 seconds
Started Aug 14 04:28:20 PM PDT 24
Finished Aug 14 04:28:24 PM PDT 24
Peak memory 191916 kb
Host smart-1a0a9ae9-28f7-48e9-b0c3-4c864a8992e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084748747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2084748747
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4100891003
Short name T416
Test name
Test status
Simulation time 428309863 ps
CPU time 2.19 seconds
Started Aug 14 04:28:30 PM PDT 24
Finished Aug 14 04:28:32 PM PDT 24
Peak memory 198548 kb
Host smart-ae2e50a1-5a46-4281-b986-8e61a91eca37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100891003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.4100891003
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3691121114
Short name T190
Test name
Test status
Simulation time 4260235756 ps
CPU time 4.15 seconds
Started Aug 14 04:28:23 PM PDT 24
Finished Aug 14 04:28:27 PM PDT 24
Peak memory 197932 kb
Host smart-d5226034-ccd4-40cb-b9b3-054a95bca53a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691121114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3691121114
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2061874741
Short name T400
Test name
Test status
Simulation time 451831273 ps
CPU time 1.31 seconds
Started Aug 14 04:28:26 PM PDT 24
Finished Aug 14 04:28:28 PM PDT 24
Peak memory 195396 kb
Host smart-9d0137b1-6914-4ebc-937c-59dba096bf6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061874741 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.2061874741
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1516118668
Short name T412
Test name
Test status
Simulation time 345031156 ps
CPU time 0.74 seconds
Started Aug 14 04:28:27 PM PDT 24
Finished Aug 14 04:28:28 PM PDT 24
Peak memory 192960 kb
Host smart-3ebb1531-aca6-4046-b541-7cbb86e1e45f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516118668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1516118668
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3609015640
Short name T287
Test name
Test status
Simulation time 485831936 ps
CPU time 0.93 seconds
Started Aug 14 04:28:26 PM PDT 24
Finished Aug 14 04:28:32 PM PDT 24
Peak memory 192864 kb
Host smart-027f7b4f-3d3c-4a74-a46a-a30cee5f31e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609015640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3609015640
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1544401157
Short name T384
Test name
Test status
Simulation time 1324861678 ps
CPU time 1.01 seconds
Started Aug 14 04:28:20 PM PDT 24
Finished Aug 14 04:28:21 PM PDT 24
Peak memory 192948 kb
Host smart-75f31662-8245-4b1d-a891-4d86bb9995f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544401157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1544401157
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2112897878
Short name T404
Test name
Test status
Simulation time 590028109 ps
CPU time 1.25 seconds
Started Aug 14 04:28:08 PM PDT 24
Finished Aug 14 04:28:10 PM PDT 24
Peak memory 198548 kb
Host smart-b11bff22-94e7-47a9-8d30-16256b1fe7cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112897878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2112897878
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3646624888
Short name T410
Test name
Test status
Simulation time 4183680883 ps
CPU time 7.45 seconds
Started Aug 14 04:28:26 PM PDT 24
Finished Aug 14 04:28:34 PM PDT 24
Peak memory 197896 kb
Host smart-34d98f6c-b4c0-46f6-97db-ce1c2ed54894
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646624888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3646624888
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1759511171
Short name T303
Test name
Test status
Simulation time 393338527 ps
CPU time 1.29 seconds
Started Aug 14 04:28:28 PM PDT 24
Finished Aug 14 04:28:30 PM PDT 24
Peak memory 196192 kb
Host smart-1491b100-192a-4820-a066-83c57a5ed202
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759511171 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1759511171
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.4198522474
Short name T393
Test name
Test status
Simulation time 557248910 ps
CPU time 0.68 seconds
Started Aug 14 04:28:24 PM PDT 24
Finished Aug 14 04:28:24 PM PDT 24
Peak memory 193256 kb
Host smart-d7ef2f7a-4d25-4d55-bdbb-eb12b6fd6c4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198522474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.4198522474
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.652247873
Short name T333
Test name
Test status
Simulation time 313504909 ps
CPU time 0.98 seconds
Started Aug 14 04:28:19 PM PDT 24
Finished Aug 14 04:28:20 PM PDT 24
Peak memory 183640 kb
Host smart-26630085-1d9e-4a3f-abdc-896e28fad5a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652247873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.652247873
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2321530718
Short name T385
Test name
Test status
Simulation time 1330357883 ps
CPU time 1.22 seconds
Started Aug 14 04:28:27 PM PDT 24
Finished Aug 14 04:28:28 PM PDT 24
Peak memory 192960 kb
Host smart-921a1218-343d-4f7f-9575-dc87672cebb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321530718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2321530718
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1056639219
Short name T334
Test name
Test status
Simulation time 932601930 ps
CPU time 1.51 seconds
Started Aug 14 04:28:15 PM PDT 24
Finished Aug 14 04:28:17 PM PDT 24
Peak memory 198568 kb
Host smart-50746189-f18f-4dc7-b99f-146274265093
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056639219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1056639219
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3106084021
Short name T189
Test name
Test status
Simulation time 4465989659 ps
CPU time 6.98 seconds
Started Aug 14 04:28:15 PM PDT 24
Finished Aug 14 04:28:22 PM PDT 24
Peak memory 197904 kb
Host smart-924a1bc1-35a1-4e26-a7fe-04026924b48c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106084021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3106084021
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2180669040
Short name T369
Test name
Test status
Simulation time 489360176 ps
CPU time 1.08 seconds
Started Aug 14 04:28:18 PM PDT 24
Finished Aug 14 04:28:19 PM PDT 24
Peak memory 198368 kb
Host smart-2acbd07f-4187-4efe-9af2-cda323800389
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180669040 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2180669040
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3407527129
Short name T50
Test name
Test status
Simulation time 500425076 ps
CPU time 0.76 seconds
Started Aug 14 04:28:12 PM PDT 24
Finished Aug 14 04:28:13 PM PDT 24
Peak memory 193056 kb
Host smart-af2b27b8-78e8-45c9-adb0-8e0237839453
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407527129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3407527129
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.4266873395
Short name T356
Test name
Test status
Simulation time 309959851 ps
CPU time 0.65 seconds
Started Aug 14 04:28:16 PM PDT 24
Finished Aug 14 04:28:16 PM PDT 24
Peak memory 183664 kb
Host smart-95de81d1-cea9-4bb6-83bd-1f642dbe0ac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266873395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.4266873395
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1392599010
Short name T66
Test name
Test status
Simulation time 1360191585 ps
CPU time 2.22 seconds
Started Aug 14 04:28:12 PM PDT 24
Finished Aug 14 04:28:14 PM PDT 24
Peak memory 193668 kb
Host smart-de7adfda-c678-4281-9726-f5899ae5da15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392599010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1392599010
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3484194105
Short name T305
Test name
Test status
Simulation time 385959992 ps
CPU time 2.02 seconds
Started Aug 14 04:28:19 PM PDT 24
Finished Aug 14 04:28:21 PM PDT 24
Peak memory 198488 kb
Host smart-1b07d7c1-1a42-4eae-87d2-d0acaf812c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484194105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3484194105
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2315162020
Short name T188
Test name
Test status
Simulation time 8459809499 ps
CPU time 14.77 seconds
Started Aug 14 04:28:13 PM PDT 24
Finished Aug 14 04:28:28 PM PDT 24
Peak memory 198208 kb
Host smart-91260cfc-d478-4cbd-a60b-b789a44d48de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315162020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2315162020
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.4199360403
Short name T72
Test name
Test status
Simulation time 540819298 ps
CPU time 0.89 seconds
Started Aug 14 04:28:05 PM PDT 24
Finished Aug 14 04:28:06 PM PDT 24
Peak memory 193964 kb
Host smart-d5d7f8ce-b5a8-45f6-92f8-b5d8f05080b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199360403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.4199360403
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.525205791
Short name T56
Test name
Test status
Simulation time 11783288595 ps
CPU time 6.64 seconds
Started Aug 14 04:28:16 PM PDT 24
Finished Aug 14 04:28:23 PM PDT 24
Peak memory 196260 kb
Host smart-8c45ecd7-da45-4d55-9afc-e7701465bc65
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525205791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.525205791
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.166849367
Short name T69
Test name
Test status
Simulation time 898545217 ps
CPU time 2.03 seconds
Started Aug 14 04:28:19 PM PDT 24
Finished Aug 14 04:28:21 PM PDT 24
Peak memory 183872 kb
Host smart-1096af9b-da03-44ee-a299-277fc057f948
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166849367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.166849367
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.986870517
Short name T40
Test name
Test status
Simulation time 456941360 ps
CPU time 1.14 seconds
Started Aug 14 04:27:45 PM PDT 24
Finished Aug 14 04:27:51 PM PDT 24
Peak memory 196056 kb
Host smart-6e944553-3d08-4af4-a498-94e47969eda7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986870517 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.986870517
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.4124610003
Short name T382
Test name
Test status
Simulation time 438377792 ps
CPU time 0.76 seconds
Started Aug 14 04:28:21 PM PDT 24
Finished Aug 14 04:28:22 PM PDT 24
Peak memory 191936 kb
Host smart-eaf6cda9-18dc-437a-80ea-62b06078110c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124610003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.4124610003
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.246580210
Short name T337
Test name
Test status
Simulation time 388715610 ps
CPU time 1.12 seconds
Started Aug 14 04:28:12 PM PDT 24
Finished Aug 14 04:28:13 PM PDT 24
Peak memory 183664 kb
Host smart-6316329f-fd1f-482e-9638-f9d55f5b1698
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246580210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.246580210
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2507180908
Short name T304
Test name
Test status
Simulation time 369492537 ps
CPU time 1.02 seconds
Started Aug 14 04:28:09 PM PDT 24
Finished Aug 14 04:28:10 PM PDT 24
Peak memory 183520 kb
Host smart-ae49feda-6ca0-498d-aeb9-26ea6d2ccbe3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507180908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2507180908
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2796870241
Short name T358
Test name
Test status
Simulation time 451949093 ps
CPU time 0.65 seconds
Started Aug 14 04:28:14 PM PDT 24
Finished Aug 14 04:28:15 PM PDT 24
Peak memory 183564 kb
Host smart-6ba1c38e-d297-4d22-aaf1-1bc253c9bd2e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796870241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2796870241
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2821394007
Short name T67
Test name
Test status
Simulation time 2390915776 ps
CPU time 5.16 seconds
Started Aug 14 04:28:06 PM PDT 24
Finished Aug 14 04:28:11 PM PDT 24
Peak memory 191936 kb
Host smart-935655c5-d6af-4eb3-940c-136a65395c02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821394007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2821394007
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2730312672
Short name T324
Test name
Test status
Simulation time 498354983 ps
CPU time 2.66 seconds
Started Aug 14 04:27:59 PM PDT 24
Finished Aug 14 04:28:02 PM PDT 24
Peak memory 198544 kb
Host smart-08e99a42-1698-4719-8ade-1c05880793c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730312672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2730312672
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3728701149
Short name T186
Test name
Test status
Simulation time 4457487436 ps
CPU time 3.77 seconds
Started Aug 14 04:28:13 PM PDT 24
Finished Aug 14 04:28:17 PM PDT 24
Peak memory 198068 kb
Host smart-a407a511-f551-43a3-be47-bb2009f1aca8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728701149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3728701149
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2602763101
Short name T336
Test name
Test status
Simulation time 301091787 ps
CPU time 0.64 seconds
Started Aug 14 04:28:14 PM PDT 24
Finished Aug 14 04:28:15 PM PDT 24
Peak memory 192900 kb
Host smart-bbb3d8aa-0a61-42a6-86db-f878529f5f67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602763101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2602763101
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.896444970
Short name T399
Test name
Test status
Simulation time 493908472 ps
CPU time 0.96 seconds
Started Aug 14 04:28:31 PM PDT 24
Finished Aug 14 04:28:32 PM PDT 24
Peak memory 192860 kb
Host smart-9c14237a-bd3f-45e5-9808-79ec736b4c30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896444970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.896444970
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1672089777
Short name T372
Test name
Test status
Simulation time 332537567 ps
CPU time 1.02 seconds
Started Aug 14 04:27:59 PM PDT 24
Finished Aug 14 04:28:00 PM PDT 24
Peak memory 183660 kb
Host smart-345bb399-b7f8-4e57-869d-03f0e8dcd21b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672089777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1672089777
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3797476654
Short name T328
Test name
Test status
Simulation time 407768414 ps
CPU time 0.9 seconds
Started Aug 14 04:28:27 PM PDT 24
Finished Aug 14 04:28:28 PM PDT 24
Peak memory 183668 kb
Host smart-7f1fe409-e3bc-4eeb-b450-533dfb398a0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797476654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3797476654
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.332582353
Short name T386
Test name
Test status
Simulation time 454799141 ps
CPU time 0.55 seconds
Started Aug 14 04:28:22 PM PDT 24
Finished Aug 14 04:28:23 PM PDT 24
Peak memory 192876 kb
Host smart-e2e8b295-ad92-417c-af2f-c8ca60e4615e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332582353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.332582353
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2057447920
Short name T367
Test name
Test status
Simulation time 348859875 ps
CPU time 0.61 seconds
Started Aug 14 04:28:30 PM PDT 24
Finished Aug 14 04:28:31 PM PDT 24
Peak memory 183676 kb
Host smart-8730814a-2217-42d5-b3de-3f0e6540f3b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057447920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2057447920
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3368000
Short name T302
Test name
Test status
Simulation time 448913306 ps
CPU time 1.18 seconds
Started Aug 14 04:28:25 PM PDT 24
Finished Aug 14 04:28:26 PM PDT 24
Peak memory 183668 kb
Host smart-d8ffb79f-aaf3-4298-9aa8-efba01075116
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3368000
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3933791773
Short name T330
Test name
Test status
Simulation time 499068488 ps
CPU time 0.69 seconds
Started Aug 14 04:28:28 PM PDT 24
Finished Aug 14 04:28:28 PM PDT 24
Peak memory 192848 kb
Host smart-ac9a4ad0-550f-4d82-bb06-d816ada009b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933791773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3933791773
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1976690227
Short name T295
Test name
Test status
Simulation time 453339356 ps
CPU time 0.99 seconds
Started Aug 14 04:28:18 PM PDT 24
Finished Aug 14 04:28:20 PM PDT 24
Peak memory 183672 kb
Host smart-7083994a-d7ac-4dce-a31e-b86fec4b516f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976690227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1976690227
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2357541078
Short name T296
Test name
Test status
Simulation time 454641983 ps
CPU time 0.83 seconds
Started Aug 14 04:28:40 PM PDT 24
Finished Aug 14 04:28:41 PM PDT 24
Peak memory 192884 kb
Host smart-a573fb6c-6732-4d11-aa5a-49358b3d8ff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357541078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2357541078
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.132829298
Short name T54
Test name
Test status
Simulation time 453338122 ps
CPU time 1.34 seconds
Started Aug 14 04:28:09 PM PDT 24
Finished Aug 14 04:28:10 PM PDT 24
Peak memory 194248 kb
Host smart-9ca5db53-5eaa-41c7-84eb-547cfbb8ad18
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132829298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.132829298
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2031544751
Short name T39
Test name
Test status
Simulation time 7493229184 ps
CPU time 2.79 seconds
Started Aug 14 04:28:04 PM PDT 24
Finished Aug 14 04:28:07 PM PDT 24
Peak memory 192164 kb
Host smart-377f65bb-592a-4e6d-8b4d-25138f62bb9b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031544751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2031544751
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3006690568
Short name T49
Test name
Test status
Simulation time 834796249 ps
CPU time 1.12 seconds
Started Aug 14 04:27:57 PM PDT 24
Finished Aug 14 04:27:58 PM PDT 24
Peak memory 192032 kb
Host smart-4a1a6e67-447e-4c2d-a50c-02b6cb061621
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006690568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3006690568
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3124442983
Short name T338
Test name
Test status
Simulation time 407402554 ps
CPU time 1.02 seconds
Started Aug 14 04:28:31 PM PDT 24
Finished Aug 14 04:28:32 PM PDT 24
Peak memory 197144 kb
Host smart-da494fca-996a-43b6-a30d-aa176f0b2634
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124442983 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3124442983
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1942998905
Short name T51
Test name
Test status
Simulation time 359800963 ps
CPU time 0.69 seconds
Started Aug 14 04:28:25 PM PDT 24
Finished Aug 14 04:28:26 PM PDT 24
Peak memory 193156 kb
Host smart-41f88d7d-6a18-48b8-8592-4400469f8d67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942998905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1942998905
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.478965377
Short name T405
Test name
Test status
Simulation time 450545631 ps
CPU time 0.96 seconds
Started Aug 14 04:28:27 PM PDT 24
Finished Aug 14 04:28:28 PM PDT 24
Peak memory 192816 kb
Host smart-ffa8c9a9-fdcf-4b22-8ffb-6c2144e6193c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478965377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.478965377
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3497567345
Short name T365
Test name
Test status
Simulation time 430267068 ps
CPU time 1.17 seconds
Started Aug 14 04:28:37 PM PDT 24
Finished Aug 14 04:28:38 PM PDT 24
Peak memory 183572 kb
Host smart-77adc99c-d646-4292-b481-2e23d5fe4765
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497567345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.3497567345
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.4023829107
Short name T329
Test name
Test status
Simulation time 267950378 ps
CPU time 0.89 seconds
Started Aug 14 04:27:57 PM PDT 24
Finished Aug 14 04:27:58 PM PDT 24
Peak memory 183544 kb
Host smart-07d1de9f-c15c-483a-a65e-c5c4df4fad8e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023829107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.4023829107
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3024957684
Short name T402
Test name
Test status
Simulation time 1135741590 ps
CPU time 0.96 seconds
Started Aug 14 04:28:23 PM PDT 24
Finished Aug 14 04:28:24 PM PDT 24
Peak memory 193992 kb
Host smart-1ed902b7-bf8d-434c-95e5-d1e195a2f5bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024957684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3024957684
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1427415835
Short name T379
Test name
Test status
Simulation time 419751181 ps
CPU time 1.77 seconds
Started Aug 14 04:28:16 PM PDT 24
Finished Aug 14 04:28:18 PM PDT 24
Peak memory 198548 kb
Host smart-a447072f-c34e-4ba0-b0ff-6d06ad3dac78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427415835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1427415835
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2769895647
Short name T403
Test name
Test status
Simulation time 3874667788 ps
CPU time 6.67 seconds
Started Aug 14 04:28:10 PM PDT 24
Finished Aug 14 04:28:16 PM PDT 24
Peak memory 196496 kb
Host smart-0d6f8343-eaf3-471f-adf7-5ea245ecf906
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769895647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.2769895647
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3292788140
Short name T361
Test name
Test status
Simulation time 503844343 ps
CPU time 0.88 seconds
Started Aug 14 04:28:34 PM PDT 24
Finished Aug 14 04:28:35 PM PDT 24
Peak memory 183652 kb
Host smart-250d312e-b0f9-45db-8eed-47079da41278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292788140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3292788140
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.526051148
Short name T353
Test name
Test status
Simulation time 487010515 ps
CPU time 1.21 seconds
Started Aug 14 04:28:34 PM PDT 24
Finished Aug 14 04:28:36 PM PDT 24
Peak memory 192864 kb
Host smart-216e3462-398b-4424-9bc2-d681c1226648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526051148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.526051148
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3156070850
Short name T396
Test name
Test status
Simulation time 333474289 ps
CPU time 1.07 seconds
Started Aug 14 04:28:26 PM PDT 24
Finished Aug 14 04:28:28 PM PDT 24
Peak memory 183624 kb
Host smart-23c3d04e-1b26-4e7a-bbb3-5c89f47f3068
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156070850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3156070850
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.961900516
Short name T343
Test name
Test status
Simulation time 333662854 ps
CPU time 0.76 seconds
Started Aug 14 04:28:23 PM PDT 24
Finished Aug 14 04:28:23 PM PDT 24
Peak memory 183596 kb
Host smart-77efc554-f074-42db-9007-7b1fd48f54c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961900516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.961900516
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1703315999
Short name T346
Test name
Test status
Simulation time 325194865 ps
CPU time 0.94 seconds
Started Aug 14 04:28:26 PM PDT 24
Finished Aug 14 04:28:27 PM PDT 24
Peak memory 192876 kb
Host smart-145d29ea-7549-4aef-a201-878e17e3662f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703315999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1703315999
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3178111008
Short name T291
Test name
Test status
Simulation time 531743191 ps
CPU time 0.61 seconds
Started Aug 14 04:28:55 PM PDT 24
Finished Aug 14 04:28:56 PM PDT 24
Peak memory 183596 kb
Host smart-e2813b28-8a3a-4c44-9707-5185d2aac258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178111008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3178111008
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.158545429
Short name T292
Test name
Test status
Simulation time 363910333 ps
CPU time 0.65 seconds
Started Aug 14 04:28:17 PM PDT 24
Finished Aug 14 04:28:18 PM PDT 24
Peak memory 183660 kb
Host smart-a5abf91a-41de-4341-986d-6540ba584d6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158545429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.158545429
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3923838227
Short name T299
Test name
Test status
Simulation time 465653941 ps
CPU time 1.17 seconds
Started Aug 14 04:28:21 PM PDT 24
Finished Aug 14 04:28:22 PM PDT 24
Peak memory 183652 kb
Host smart-9d6c9ea3-de05-4724-8ee6-6a9b35c07774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923838227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3923838227
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.626273593
Short name T342
Test name
Test status
Simulation time 347974902 ps
CPU time 1.09 seconds
Started Aug 14 04:28:30 PM PDT 24
Finished Aug 14 04:28:31 PM PDT 24
Peak memory 183640 kb
Host smart-d559491e-514c-4dcf-ba8a-109b5936e033
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626273593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.626273593
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2313432828
Short name T293
Test name
Test status
Simulation time 412077860 ps
CPU time 0.87 seconds
Started Aug 14 04:28:27 PM PDT 24
Finished Aug 14 04:28:28 PM PDT 24
Peak memory 192880 kb
Host smart-4a035b58-597d-431c-965c-8fa4f7cf7c09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313432828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2313432828
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2223688304
Short name T318
Test name
Test status
Simulation time 550152037 ps
CPU time 0.89 seconds
Started Aug 14 04:28:23 PM PDT 24
Finished Aug 14 04:28:24 PM PDT 24
Peak memory 193188 kb
Host smart-0bcc3b99-0efd-4043-8dab-800fdd4d4b1f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223688304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2223688304
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.325140904
Short name T38
Test name
Test status
Simulation time 14427516238 ps
CPU time 6.17 seconds
Started Aug 14 04:28:30 PM PDT 24
Finished Aug 14 04:28:36 PM PDT 24
Peak memory 192196 kb
Host smart-625bf26f-0052-4994-8676-91325b0daf59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325140904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.325140904
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3969363855
Short name T357
Test name
Test status
Simulation time 784241770 ps
CPU time 1.62 seconds
Started Aug 14 04:28:00 PM PDT 24
Finished Aug 14 04:28:02 PM PDT 24
Peak memory 183708 kb
Host smart-1b87e34e-094a-479c-b041-dd7560d5fb29
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969363855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3969363855
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3266695626
Short name T387
Test name
Test status
Simulation time 372705890 ps
CPU time 0.89 seconds
Started Aug 14 04:28:02 PM PDT 24
Finished Aug 14 04:28:03 PM PDT 24
Peak memory 196132 kb
Host smart-3b57e8a8-8723-4a99-a66d-45fc9c1d7389
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266695626 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3266695626
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2903690145
Short name T58
Test name
Test status
Simulation time 451286280 ps
CPU time 0.68 seconds
Started Aug 14 04:27:46 PM PDT 24
Finished Aug 14 04:27:46 PM PDT 24
Peak memory 193180 kb
Host smart-112ce07d-13fc-4612-8830-3373cd91b871
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903690145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2903690145
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.84757439
Short name T392
Test name
Test status
Simulation time 437597296 ps
CPU time 0.72 seconds
Started Aug 14 04:28:26 PM PDT 24
Finished Aug 14 04:28:27 PM PDT 24
Peak memory 183656 kb
Host smart-e1539c4a-0446-481e-8763-689f02ea0804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84757439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.84757439
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2703749278
Short name T350
Test name
Test status
Simulation time 480843603 ps
CPU time 0.62 seconds
Started Aug 14 04:28:11 PM PDT 24
Finished Aug 14 04:28:11 PM PDT 24
Peak memory 183592 kb
Host smart-367ae4d1-78ff-436c-9110-a3445423b661
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703749278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.2703749278
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3761091160
Short name T373
Test name
Test status
Simulation time 324489914 ps
CPU time 0.73 seconds
Started Aug 14 04:28:03 PM PDT 24
Finished Aug 14 04:28:03 PM PDT 24
Peak memory 183580 kb
Host smart-5b5b5964-86a8-4836-9347-3278f4bf07ff
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761091160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3761091160
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3790447590
Short name T60
Test name
Test status
Simulation time 2164016466 ps
CPU time 0.95 seconds
Started Aug 14 04:28:05 PM PDT 24
Finished Aug 14 04:28:06 PM PDT 24
Peak memory 184032 kb
Host smart-0b64e98a-68ec-40e3-8699-4c82a271e7e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790447590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3790447590
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.4269403327
Short name T314
Test name
Test status
Simulation time 735383475 ps
CPU time 1.58 seconds
Started Aug 14 04:28:24 PM PDT 24
Finished Aug 14 04:28:26 PM PDT 24
Peak memory 198384 kb
Host smart-90935f46-b7d8-4073-b40a-90ea19fa486a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269403327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.4269403327
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2929391427
Short name T327
Test name
Test status
Simulation time 4284052301 ps
CPU time 6.43 seconds
Started Aug 14 04:28:21 PM PDT 24
Finished Aug 14 04:28:28 PM PDT 24
Peak memory 197716 kb
Host smart-9343cc8b-258e-4d70-9dd7-4ee76e3b2ad6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929391427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2929391427
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2509872795
Short name T307
Test name
Test status
Simulation time 499790622 ps
CPU time 0.72 seconds
Started Aug 14 04:28:14 PM PDT 24
Finished Aug 14 04:28:15 PM PDT 24
Peak memory 192804 kb
Host smart-ca63a626-e1eb-45a8-89be-2bec6226e53c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509872795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2509872795
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.91034525
Short name T414
Test name
Test status
Simulation time 479914812 ps
CPU time 1.37 seconds
Started Aug 14 04:28:42 PM PDT 24
Finished Aug 14 04:28:43 PM PDT 24
Peak memory 192876 kb
Host smart-6d567018-4292-490c-a2df-4f2169dd6c8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91034525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.91034525
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2364914291
Short name T310
Test name
Test status
Simulation time 621965333 ps
CPU time 0.59 seconds
Started Aug 14 04:28:22 PM PDT 24
Finished Aug 14 04:28:23 PM PDT 24
Peak memory 192884 kb
Host smart-c3b43f11-ba35-43d0-9186-3d008b69b69c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364914291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2364914291
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.193504357
Short name T381
Test name
Test status
Simulation time 358673081 ps
CPU time 0.68 seconds
Started Aug 14 04:28:23 PM PDT 24
Finished Aug 14 04:28:24 PM PDT 24
Peak memory 183680 kb
Host smart-8df464a3-6b67-4a28-a586-e9c64f003aca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193504357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.193504357
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3824931919
Short name T420
Test name
Test status
Simulation time 394697497 ps
CPU time 0.81 seconds
Started Aug 14 04:28:32 PM PDT 24
Finished Aug 14 04:28:33 PM PDT 24
Peak memory 183680 kb
Host smart-42ffefa3-0259-4bad-8ffd-d7f224c06921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824931919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3824931919
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1171830441
Short name T325
Test name
Test status
Simulation time 295269619 ps
CPU time 0.96 seconds
Started Aug 14 04:28:26 PM PDT 24
Finished Aug 14 04:28:27 PM PDT 24
Peak memory 183668 kb
Host smart-089877f9-1ba2-478e-82e3-5080e6c4c99c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171830441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1171830441
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1235998456
Short name T376
Test name
Test status
Simulation time 476787906 ps
CPU time 0.58 seconds
Started Aug 14 04:28:32 PM PDT 24
Finished Aug 14 04:28:33 PM PDT 24
Peak memory 183600 kb
Host smart-6cd53d86-37e5-4f4e-99c8-0095fcabf9ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235998456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1235998456
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1702788038
Short name T360
Test name
Test status
Simulation time 450997169 ps
CPU time 0.68 seconds
Started Aug 14 04:29:36 PM PDT 24
Finished Aug 14 04:29:37 PM PDT 24
Peak memory 183640 kb
Host smart-cc0516b1-1f2c-43a1-94be-02da0786b971
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702788038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1702788038
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1923202176
Short name T345
Test name
Test status
Simulation time 378868484 ps
CPU time 1.13 seconds
Started Aug 14 04:28:33 PM PDT 24
Finished Aug 14 04:28:34 PM PDT 24
Peak memory 192968 kb
Host smart-2b1d4136-188c-47fa-a9e0-0d769625d64c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923202176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1923202176
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.522352199
Short name T391
Test name
Test status
Simulation time 326517591 ps
CPU time 0.58 seconds
Started Aug 14 04:28:45 PM PDT 24
Finished Aug 14 04:28:45 PM PDT 24
Peak memory 192900 kb
Host smart-88e3a7e1-0536-4f4d-9aee-808e2f8d3276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522352199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.522352199
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2423933935
Short name T335
Test name
Test status
Simulation time 378551448 ps
CPU time 1.23 seconds
Started Aug 14 04:28:13 PM PDT 24
Finished Aug 14 04:28:14 PM PDT 24
Peak memory 195652 kb
Host smart-a0bd22d7-36af-4d52-b1fe-255a993f4ebb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423933935 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2423933935
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1747413548
Short name T370
Test name
Test status
Simulation time 423698680 ps
CPU time 0.92 seconds
Started Aug 14 04:27:55 PM PDT 24
Finished Aug 14 04:27:56 PM PDT 24
Peak memory 193136 kb
Host smart-e57337dc-d570-4920-a82d-bce32d8d404f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747413548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1747413548
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1500613995
Short name T306
Test name
Test status
Simulation time 380915125 ps
CPU time 0.8 seconds
Started Aug 14 04:28:24 PM PDT 24
Finished Aug 14 04:28:25 PM PDT 24
Peak memory 192876 kb
Host smart-bb3e5348-16b3-4c49-a07f-606e9bdd898a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500613995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1500613995
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.648077763
Short name T62
Test name
Test status
Simulation time 1363645901 ps
CPU time 3.93 seconds
Started Aug 14 04:28:12 PM PDT 24
Finished Aug 14 04:28:16 PM PDT 24
Peak memory 193956 kb
Host smart-8ce23ad0-5348-4970-828d-ea96966dbbb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648077763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.648077763
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2102075134
Short name T297
Test name
Test status
Simulation time 581965440 ps
CPU time 1.87 seconds
Started Aug 14 04:28:10 PM PDT 24
Finished Aug 14 04:28:12 PM PDT 24
Peak memory 198508 kb
Host smart-f4a6933b-28cd-4f63-a4ee-b0aa205eca66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102075134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2102075134
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2975819424
Short name T185
Test name
Test status
Simulation time 4832703078 ps
CPU time 2.34 seconds
Started Aug 14 04:28:06 PM PDT 24
Finished Aug 14 04:28:09 PM PDT 24
Peak memory 197816 kb
Host smart-2c59b8e3-e830-414a-8a65-598005df53fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975819424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2975819424
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.676131595
Short name T340
Test name
Test status
Simulation time 526667200 ps
CPU time 0.83 seconds
Started Aug 14 04:27:56 PM PDT 24
Finished Aug 14 04:27:57 PM PDT 24
Peak memory 196416 kb
Host smart-29d5a50b-28b9-4b3a-a0ac-f2349d5e6168
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676131595 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.676131595
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3334723465
Short name T323
Test name
Test status
Simulation time 468628150 ps
CPU time 0.71 seconds
Started Aug 14 04:28:08 PM PDT 24
Finished Aug 14 04:28:09 PM PDT 24
Peak memory 193960 kb
Host smart-72f057f0-63f8-40db-8a3f-424fe8547bc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334723465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3334723465
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1406284398
Short name T341
Test name
Test status
Simulation time 409292531 ps
CPU time 0.69 seconds
Started Aug 14 04:28:04 PM PDT 24
Finished Aug 14 04:28:05 PM PDT 24
Peak memory 183616 kb
Host smart-6048e3d1-e3b4-4ec6-85d7-064ee4841c56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406284398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1406284398
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.152680877
Short name T61
Test name
Test status
Simulation time 1423437650 ps
CPU time 1.26 seconds
Started Aug 14 04:28:06 PM PDT 24
Finished Aug 14 04:28:07 PM PDT 24
Peak memory 193148 kb
Host smart-aad92080-1122-4295-9a00-d5df1343b04f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152680877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.152680877
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2044924573
Short name T419
Test name
Test status
Simulation time 468949265 ps
CPU time 2.17 seconds
Started Aug 14 04:28:08 PM PDT 24
Finished Aug 14 04:28:11 PM PDT 24
Peak memory 198520 kb
Host smart-888f7f68-2001-483e-9953-1c8e2ed7007d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044924573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2044924573
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.641301269
Short name T407
Test name
Test status
Simulation time 391277853 ps
CPU time 0.71 seconds
Started Aug 14 04:28:01 PM PDT 24
Finished Aug 14 04:28:02 PM PDT 24
Peak memory 195680 kb
Host smart-e26b91c8-c035-4159-b224-aee0c36f1cf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641301269 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.641301269
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3560459825
Short name T421
Test name
Test status
Simulation time 322884153 ps
CPU time 0.67 seconds
Started Aug 14 04:28:05 PM PDT 24
Finished Aug 14 04:28:06 PM PDT 24
Peak memory 192932 kb
Host smart-ab73ef4f-2a94-4225-9829-f192b88afd3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560459825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3560459825
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1950972245
Short name T312
Test name
Test status
Simulation time 423697990 ps
CPU time 0.85 seconds
Started Aug 14 04:28:14 PM PDT 24
Finished Aug 14 04:28:15 PM PDT 24
Peak memory 192848 kb
Host smart-e8f3e0fe-99e7-4717-a626-70f16abe760f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950972245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1950972245
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3652169301
Short name T65
Test name
Test status
Simulation time 3175537401 ps
CPU time 1 seconds
Started Aug 14 04:28:06 PM PDT 24
Finished Aug 14 04:28:12 PM PDT 24
Peak memory 195316 kb
Host smart-2e6dc6a3-2c5e-48c1-aee6-9c246a795b2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652169301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3652169301
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2950504325
Short name T320
Test name
Test status
Simulation time 455208974 ps
CPU time 1.78 seconds
Started Aug 14 04:28:24 PM PDT 24
Finished Aug 14 04:28:26 PM PDT 24
Peak memory 198532 kb
Host smart-5a78f34a-58d4-44d7-834b-d43744419040
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950504325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2950504325
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1258762283
Short name T35
Test name
Test status
Simulation time 4292540384 ps
CPU time 3.72 seconds
Started Aug 14 04:28:13 PM PDT 24
Finished Aug 14 04:28:17 PM PDT 24
Peak memory 197588 kb
Host smart-4c258455-5123-4a5e-aa57-4ae3fce0129e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258762283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1258762283
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1798642403
Short name T352
Test name
Test status
Simulation time 347467737 ps
CPU time 0.73 seconds
Started Aug 14 04:28:09 PM PDT 24
Finished Aug 14 04:28:10 PM PDT 24
Peak memory 196004 kb
Host smart-356f76bf-dd8e-4e28-b98c-92b43b7bb53d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798642403 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1798642403
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1405347326
Short name T375
Test name
Test status
Simulation time 324699093 ps
CPU time 0.81 seconds
Started Aug 14 04:28:22 PM PDT 24
Finished Aug 14 04:28:23 PM PDT 24
Peak memory 191984 kb
Host smart-efa878ca-60ca-4400-baf7-011c52353124
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405347326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1405347326
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.349744201
Short name T322
Test name
Test status
Simulation time 575766641 ps
CPU time 0.62 seconds
Started Aug 14 04:28:23 PM PDT 24
Finished Aug 14 04:28:24 PM PDT 24
Peak memory 183604 kb
Host smart-70ac2399-c395-4e83-8873-4fd9a0f032a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349744201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.349744201
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2887044261
Short name T344
Test name
Test status
Simulation time 1894234156 ps
CPU time 2.22 seconds
Started Aug 14 04:28:04 PM PDT 24
Finished Aug 14 04:28:06 PM PDT 24
Peak memory 193988 kb
Host smart-133c1ac9-3289-426b-a708-8c588f893c97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887044261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2887044261
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2342195331
Short name T389
Test name
Test status
Simulation time 346540179 ps
CPU time 1.51 seconds
Started Aug 14 04:28:01 PM PDT 24
Finished Aug 14 04:28:03 PM PDT 24
Peak memory 198140 kb
Host smart-2a9082b1-56df-4b00-9111-7a99d5e9c6bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342195331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2342195331
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3206313166
Short name T319
Test name
Test status
Simulation time 4266445158 ps
CPU time 2.27 seconds
Started Aug 14 04:28:03 PM PDT 24
Finished Aug 14 04:28:06 PM PDT 24
Peak memory 196404 kb
Host smart-9aaffb9e-42cc-47f3-8d10-5252cc923917
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206313166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3206313166
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3095762086
Short name T37
Test name
Test status
Simulation time 539651872 ps
CPU time 0.83 seconds
Started Aug 14 04:28:15 PM PDT 24
Finished Aug 14 04:28:16 PM PDT 24
Peak memory 196264 kb
Host smart-bb60c7f9-5295-4c45-86ed-c0728b76e3fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095762086 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3095762086
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3648921685
Short name T351
Test name
Test status
Simulation time 538247463 ps
CPU time 0.73 seconds
Started Aug 14 04:28:08 PM PDT 24
Finished Aug 14 04:28:09 PM PDT 24
Peak memory 191984 kb
Host smart-1bd33e46-bc0f-4c17-a327-35f1e7600a9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648921685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3648921685
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3123171665
Short name T311
Test name
Test status
Simulation time 522227639 ps
CPU time 0.84 seconds
Started Aug 14 04:28:27 PM PDT 24
Finished Aug 14 04:28:28 PM PDT 24
Peak memory 183664 kb
Host smart-35134e61-cf58-4c61-b3a5-9895e754f448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123171665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3123171665
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.515662899
Short name T383
Test name
Test status
Simulation time 1779968539 ps
CPU time 3.86 seconds
Started Aug 14 04:28:09 PM PDT 24
Finished Aug 14 04:28:13 PM PDT 24
Peak memory 183968 kb
Host smart-2f5d6510-1791-4873-8a7b-4222bdabd5a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515662899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.515662899
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3240169782
Short name T288
Test name
Test status
Simulation time 532595743 ps
CPU time 1.99 seconds
Started Aug 14 04:28:16 PM PDT 24
Finished Aug 14 04:28:18 PM PDT 24
Peak memory 198508 kb
Host smart-6735eccb-ba7c-40b0-bd2e-2bd6d2c1a0d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240169782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3240169782
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1904050903
Short name T237
Test name
Test status
Simulation time 56001856911 ps
CPU time 22.44 seconds
Started Aug 14 04:31:28 PM PDT 24
Finished Aug 14 04:31:51 PM PDT 24
Peak memory 197080 kb
Host smart-5cda63c2-1a71-48b5-af40-a9f9db6b949d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904050903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1904050903
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.312641428
Short name T220
Test name
Test status
Simulation time 439027464 ps
CPU time 0.82 seconds
Started Aug 14 04:31:18 PM PDT 24
Finished Aug 14 04:31:19 PM PDT 24
Peak memory 192016 kb
Host smart-57151d73-a792-4582-a285-974675e70c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312641428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.312641428
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1213948156
Short name T195
Test name
Test status
Simulation time 31038499183 ps
CPU time 13.35 seconds
Started Aug 14 04:31:25 PM PDT 24
Finished Aug 14 04:31:38 PM PDT 24
Peak memory 192084 kb
Host smart-5458bb86-066a-4d53-a435-46c322036c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213948156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1213948156
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2600849057
Short name T17
Test name
Test status
Simulation time 4432998253 ps
CPU time 2.25 seconds
Started Aug 14 04:31:39 PM PDT 24
Finished Aug 14 04:31:42 PM PDT 24
Peak memory 216152 kb
Host smart-b9bab22a-c33b-470d-828e-a0f297a2a850
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600849057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2600849057
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3017038344
Short name T211
Test name
Test status
Simulation time 446492243 ps
CPU time 1.19 seconds
Started Aug 14 04:31:15 PM PDT 24
Finished Aug 14 04:31:17 PM PDT 24
Peak memory 196864 kb
Host smart-3ab86e09-ffd6-4dfd-941e-32606d4aefca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017038344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3017038344
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3434528560
Short name T239
Test name
Test status
Simulation time 21585846151 ps
CPU time 32.27 seconds
Started Aug 14 04:31:44 PM PDT 24
Finished Aug 14 04:32:16 PM PDT 24
Peak memory 197160 kb
Host smart-7115ba36-826a-4452-ac56-3e5b53054dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434528560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3434528560
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.4057539233
Short name T227
Test name
Test status
Simulation time 491736459 ps
CPU time 0.75 seconds
Started Aug 14 04:31:39 PM PDT 24
Finished Aug 14 04:31:40 PM PDT 24
Peak memory 196824 kb
Host smart-97bf0874-816b-45cc-a047-c9a63a2fdccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057539233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.4057539233
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.8973290
Short name T238
Test name
Test status
Simulation time 56921080434 ps
CPU time 43.02 seconds
Started Aug 14 04:31:30 PM PDT 24
Finished Aug 14 04:32:19 PM PDT 24
Peak memory 192092 kb
Host smart-245125c5-afd9-4f68-9233-6e8a09063ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8973290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.8973290
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.762559987
Short name T229
Test name
Test status
Simulation time 534040533 ps
CPU time 0.97 seconds
Started Aug 14 04:31:33 PM PDT 24
Finished Aug 14 04:31:34 PM PDT 24
Peak memory 196764 kb
Host smart-05d663ec-e83d-4b3e-bbc6-1217ef9f217a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762559987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.762559987
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3762548391
Short name T153
Test name
Test status
Simulation time 126560239382 ps
CPU time 179.25 seconds
Started Aug 14 04:31:32 PM PDT 24
Finished Aug 14 04:34:31 PM PDT 24
Peak memory 192064 kb
Host smart-27245c04-b211-491d-867a-12b3eb310d2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762548391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3762548391
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1332102944
Short name T250
Test name
Test status
Simulation time 51285987722 ps
CPU time 66.36 seconds
Started Aug 14 04:31:41 PM PDT 24
Finished Aug 14 04:32:47 PM PDT 24
Peak memory 192096 kb
Host smart-48c30e78-a507-46b6-bef9-d5522d0c7065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332102944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1332102944
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.281281544
Short name T266
Test name
Test status
Simulation time 482095566 ps
CPU time 0.74 seconds
Started Aug 14 04:31:43 PM PDT 24
Finished Aug 14 04:31:44 PM PDT 24
Peak memory 192012 kb
Host smart-e1f6d3c4-dd3c-4f6d-a71a-c2626c6486c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281281544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.281281544
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.2186325041
Short name T194
Test name
Test status
Simulation time 23858990692 ps
CPU time 2.95 seconds
Started Aug 14 04:31:39 PM PDT 24
Finished Aug 14 04:31:42 PM PDT 24
Peak memory 192080 kb
Host smart-6353979a-2f90-4e99-a515-c44be9fe79c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186325041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2186325041
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3259358887
Short name T222
Test name
Test status
Simulation time 601254300 ps
CPU time 0.65 seconds
Started Aug 14 04:31:36 PM PDT 24
Finished Aug 14 04:31:37 PM PDT 24
Peak memory 191996 kb
Host smart-d92e4b54-b886-4eee-aa67-9203d45d6aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259358887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3259358887
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3810549595
Short name T277
Test name
Test status
Simulation time 28873646979 ps
CPU time 8.09 seconds
Started Aug 14 04:32:03 PM PDT 24
Finished Aug 14 04:32:11 PM PDT 24
Peak memory 192104 kb
Host smart-86d398a0-f86e-422e-b4f4-553a1562a81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810549595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3810549595
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.1904462154
Short name T270
Test name
Test status
Simulation time 575180994 ps
CPU time 1.18 seconds
Started Aug 14 04:31:34 PM PDT 24
Finished Aug 14 04:31:35 PM PDT 24
Peak memory 191996 kb
Host smart-460c2ecc-4327-4f4c-9fed-43ace2f5fe55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904462154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1904462154
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3689617423
Short name T2
Test name
Test status
Simulation time 25218704163 ps
CPU time 37.76 seconds
Started Aug 14 04:31:28 PM PDT 24
Finished Aug 14 04:32:06 PM PDT 24
Peak memory 192064 kb
Host smart-f7743bea-b3b8-408f-9a99-d45ff96c030e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689617423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3689617423
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3872643459
Short name T272
Test name
Test status
Simulation time 472981412 ps
CPU time 0.9 seconds
Started Aug 14 04:31:46 PM PDT 24
Finished Aug 14 04:31:47 PM PDT 24
Peak memory 191992 kb
Host smart-55698af5-7c8c-4003-a283-569bfc39995f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872643459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3872643459
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1568995361
Short name T182
Test name
Test status
Simulation time 2174978513 ps
CPU time 4.02 seconds
Started Aug 14 04:31:50 PM PDT 24
Finished Aug 14 04:31:54 PM PDT 24
Peak memory 198752 kb
Host smart-d9d06bf9-1e21-4d62-98bf-486da773c16b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568995361 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1568995361
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1456589859
Short name T284
Test name
Test status
Simulation time 4272944295 ps
CPU time 3.33 seconds
Started Aug 14 04:31:46 PM PDT 24
Finished Aug 14 04:31:49 PM PDT 24
Peak memory 196876 kb
Host smart-5bd4ba15-e778-4aee-afae-aa66f2e5accf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456589859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1456589859
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.632313113
Short name T247
Test name
Test status
Simulation time 459978181 ps
CPU time 0.97 seconds
Started Aug 14 04:31:38 PM PDT 24
Finished Aug 14 04:31:39 PM PDT 24
Peak memory 191992 kb
Host smart-10b1471a-5fb2-4ab5-a8cf-a171493362da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632313113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.632313113
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2368559411
Short name T217
Test name
Test status
Simulation time 17862284586 ps
CPU time 6.39 seconds
Started Aug 14 04:31:50 PM PDT 24
Finished Aug 14 04:31:56 PM PDT 24
Peak memory 192060 kb
Host smart-d1474c88-2e4c-4224-9927-0b52ef28185d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368559411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2368559411
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.4146567737
Short name T198
Test name
Test status
Simulation time 563837421 ps
CPU time 1.38 seconds
Started Aug 14 04:31:34 PM PDT 24
Finished Aug 14 04:31:35 PM PDT 24
Peak memory 196836 kb
Host smart-c2b86263-e42e-47cf-8e0a-6de8fd5d2bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146567737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.4146567737
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.4139594126
Short name T264
Test name
Test status
Simulation time 14763648644 ps
CPU time 22.2 seconds
Started Aug 14 04:31:41 PM PDT 24
Finished Aug 14 04:32:03 PM PDT 24
Peak memory 197092 kb
Host smart-b3f870d3-d30d-480e-bba6-20d86a1ec730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139594126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.4139594126
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3988176916
Short name T205
Test name
Test status
Simulation time 604454290 ps
CPU time 0.78 seconds
Started Aug 14 04:31:30 PM PDT 24
Finished Aug 14 04:31:31 PM PDT 24
Peak memory 192008 kb
Host smart-dd6fcddc-95ea-4c11-8453-bfc2045115a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988176916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3988176916
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1808087725
Short name T74
Test name
Test status
Simulation time 1306580318 ps
CPU time 7.41 seconds
Started Aug 14 04:31:36 PM PDT 24
Finished Aug 14 04:31:44 PM PDT 24
Peak memory 198676 kb
Host smart-6993ab9c-5fc3-4bfd-9e7d-eb2667ed20da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808087725 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1808087725
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1306819495
Short name T244
Test name
Test status
Simulation time 18374906625 ps
CPU time 14.55 seconds
Started Aug 14 04:31:42 PM PDT 24
Finished Aug 14 04:31:57 PM PDT 24
Peak memory 192164 kb
Host smart-6a76a0a0-df87-4930-8b85-8fd4feda1e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306819495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1306819495
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3176465380
Short name T245
Test name
Test status
Simulation time 342661221 ps
CPU time 1.05 seconds
Started Aug 14 04:31:39 PM PDT 24
Finished Aug 14 04:31:40 PM PDT 24
Peak memory 196784 kb
Host smart-47889c44-a0a5-4513-85a4-db86bf9e13ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176465380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3176465380
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3377979795
Short name T251
Test name
Test status
Simulation time 37388806375 ps
CPU time 49.58 seconds
Started Aug 14 04:31:37 PM PDT 24
Finished Aug 14 04:32:27 PM PDT 24
Peak memory 192068 kb
Host smart-56f1f176-e2da-4cb3-a12a-c6999b1ef8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377979795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3377979795
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2078089495
Short name T21
Test name
Test status
Simulation time 7517148193 ps
CPU time 6.16 seconds
Started Aug 14 04:31:24 PM PDT 24
Finished Aug 14 04:31:30 PM PDT 24
Peak memory 216248 kb
Host smart-00b55bb2-8a1a-4ece-b163-bef4a105c7db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078089495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2078089495
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1117543865
Short name T204
Test name
Test status
Simulation time 605004074 ps
CPU time 0.64 seconds
Started Aug 14 04:31:37 PM PDT 24
Finished Aug 14 04:31:38 PM PDT 24
Peak memory 192012 kb
Host smart-f5d3f6ca-b3e7-4d16-9137-65a1e01b7e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117543865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1117543865
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2243433481
Short name T214
Test name
Test status
Simulation time 56622263232 ps
CPU time 37.48 seconds
Started Aug 14 04:31:51 PM PDT 24
Finished Aug 14 04:32:29 PM PDT 24
Peak memory 192056 kb
Host smart-f74981a1-2f02-4384-9e6a-1d6023cab2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243433481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2243433481
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.257131198
Short name T279
Test name
Test status
Simulation time 406515800 ps
CPU time 1.15 seconds
Started Aug 14 04:31:41 PM PDT 24
Finished Aug 14 04:31:42 PM PDT 24
Peak memory 196868 kb
Host smart-b8e997d1-ddb9-4c1d-87b7-cf33b0133efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257131198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.257131198
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2117918691
Short name T233
Test name
Test status
Simulation time 47496008892 ps
CPU time 71.35 seconds
Started Aug 14 04:31:42 PM PDT 24
Finished Aug 14 04:32:53 PM PDT 24
Peak memory 197128 kb
Host smart-fae8880d-7d76-4316-82bc-3d93f7d877ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117918691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2117918691
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3105805310
Short name T200
Test name
Test status
Simulation time 606328642 ps
CPU time 0.64 seconds
Started Aug 14 04:31:54 PM PDT 24
Finished Aug 14 04:31:55 PM PDT 24
Peak memory 196848 kb
Host smart-d1411834-b244-48a1-96fd-34393eb6c01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105805310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3105805310
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3274460355
Short name T258
Test name
Test status
Simulation time 33613296916 ps
CPU time 12.95 seconds
Started Aug 14 04:31:43 PM PDT 24
Finished Aug 14 04:31:56 PM PDT 24
Peak memory 192060 kb
Host smart-fa6939bc-c84c-4779-8757-a2a8701c5330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274460355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3274460355
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.237695786
Short name T246
Test name
Test status
Simulation time 487117351 ps
CPU time 1.23 seconds
Started Aug 14 04:31:24 PM PDT 24
Finished Aug 14 04:31:26 PM PDT 24
Peak memory 192032 kb
Host smart-3f9670dd-23ce-42d1-8ef5-7d87eeb34828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237695786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.237695786
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2531804969
Short name T267
Test name
Test status
Simulation time 11334920626 ps
CPU time 16.05 seconds
Started Aug 14 04:32:34 PM PDT 24
Finished Aug 14 04:32:50 PM PDT 24
Peak memory 192060 kb
Host smart-5af027dc-beda-427f-8aca-f2ce8f29bf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531804969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2531804969
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.3847832160
Short name T259
Test name
Test status
Simulation time 451498977 ps
CPU time 0.89 seconds
Started Aug 14 04:31:53 PM PDT 24
Finished Aug 14 04:31:54 PM PDT 24
Peak memory 196732 kb
Host smart-92f86381-0b18-495f-99b3-17a3d7edda44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847832160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3847832160
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2012599227
Short name T12
Test name
Test status
Simulation time 42603602353 ps
CPU time 52.21 seconds
Started Aug 14 04:32:10 PM PDT 24
Finished Aug 14 04:33:02 PM PDT 24
Peak memory 192084 kb
Host smart-7d87c772-7067-4628-9124-53961f2a754d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012599227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2012599227
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.4045605796
Short name T274
Test name
Test status
Simulation time 470956982 ps
CPU time 1.2 seconds
Started Aug 14 04:32:06 PM PDT 24
Finished Aug 14 04:32:07 PM PDT 24
Peak memory 196776 kb
Host smart-29f8c868-3d19-4b1d-8afc-cbe6bf4de156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045605796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.4045605796
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.2951069170
Short name T9
Test name
Test status
Simulation time 45704569364 ps
CPU time 64.13 seconds
Started Aug 14 04:31:49 PM PDT 24
Finished Aug 14 04:32:53 PM PDT 24
Peak memory 192104 kb
Host smart-44650b61-cc65-43fc-b873-dda072179359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951069170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2951069170
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3832231749
Short name T286
Test name
Test status
Simulation time 590305943 ps
CPU time 0.61 seconds
Started Aug 14 04:31:54 PM PDT 24
Finished Aug 14 04:31:55 PM PDT 24
Peak memory 192016 kb
Host smart-ff98b930-8f74-43d6-a959-d872bff0b2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832231749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3832231749
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3001160908
Short name T282
Test name
Test status
Simulation time 2089083402 ps
CPU time 7.7 seconds
Started Aug 14 04:31:57 PM PDT 24
Finished Aug 14 04:32:04 PM PDT 24
Peak memory 206848 kb
Host smart-de719131-3c58-4902-bdbd-1de2c7726943
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001160908 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3001160908
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3746574365
Short name T231
Test name
Test status
Simulation time 5446844739 ps
CPU time 4.18 seconds
Started Aug 14 04:31:55 PM PDT 24
Finished Aug 14 04:32:04 PM PDT 24
Peak memory 192060 kb
Host smart-68f3a979-27e2-40d7-80c6-97add600bb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746574365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3746574365
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3750386186
Short name T273
Test name
Test status
Simulation time 504381509 ps
CPU time 1.38 seconds
Started Aug 14 04:31:26 PM PDT 24
Finished Aug 14 04:31:27 PM PDT 24
Peak memory 196928 kb
Host smart-c2498b91-9a96-45b5-9007-56189720d4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750386186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3750386186
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2755392400
Short name T242
Test name
Test status
Simulation time 13777960064 ps
CPU time 3.61 seconds
Started Aug 14 04:31:56 PM PDT 24
Finished Aug 14 04:32:00 PM PDT 24
Peak memory 197100 kb
Host smart-8670ffd3-60cd-4b59-a1e8-4427657bfbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755392400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2755392400
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3302862585
Short name T22
Test name
Test status
Simulation time 510667037 ps
CPU time 0.67 seconds
Started Aug 14 04:31:47 PM PDT 24
Finished Aug 14 04:31:48 PM PDT 24
Peak memory 192016 kb
Host smart-4b7efdd8-5aff-4df6-b3c0-abe37ab7b768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302862585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3302862585
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2019825653
Short name T223
Test name
Test status
Simulation time 3006552197 ps
CPU time 2.63 seconds
Started Aug 14 04:31:51 PM PDT 24
Finished Aug 14 04:31:54 PM PDT 24
Peak memory 192064 kb
Host smart-2b430d5d-1e88-49c7-b0e5-640c7327ba88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019825653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2019825653
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.350847081
Short name T216
Test name
Test status
Simulation time 698790986 ps
CPU time 0.61 seconds
Started Aug 14 04:31:54 PM PDT 24
Finished Aug 14 04:31:54 PM PDT 24
Peak memory 196800 kb
Host smart-13083799-9c0c-4dfc-9f91-3bb15b687fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350847081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.350847081
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2362751145
Short name T193
Test name
Test status
Simulation time 21460001179 ps
CPU time 2.21 seconds
Started Aug 14 04:31:47 PM PDT 24
Finished Aug 14 04:31:49 PM PDT 24
Peak memory 192084 kb
Host smart-6a374845-a0d4-4c6e-9c96-6b011351302d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362751145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2362751145
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.406605127
Short name T207
Test name
Test status
Simulation time 607658915 ps
CPU time 1 seconds
Started Aug 14 04:32:15 PM PDT 24
Finished Aug 14 04:32:16 PM PDT 24
Peak memory 192016 kb
Host smart-1a09c724-6fa5-4ef1-82e3-e2587835a7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406605127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.406605127
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3426290227
Short name T41
Test name
Test status
Simulation time 10504759338 ps
CPU time 17.09 seconds
Started Aug 14 04:32:09 PM PDT 24
Finished Aug 14 04:32:26 PM PDT 24
Peak memory 198960 kb
Host smart-7bb7cd68-3562-47ea-99f3-cc8b70242276
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426290227 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3426290227
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3604147908
Short name T261
Test name
Test status
Simulation time 32866844072 ps
CPU time 33.63 seconds
Started Aug 14 04:31:21 PM PDT 24
Finished Aug 14 04:31:55 PM PDT 24
Peak memory 192040 kb
Host smart-bfa6d878-eb6b-4208-b92e-ad49436c11a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604147908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3604147908
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1123466807
Short name T20
Test name
Test status
Simulation time 4019662364 ps
CPU time 6.52 seconds
Started Aug 14 04:31:18 PM PDT 24
Finished Aug 14 04:31:25 PM PDT 24
Peak memory 215780 kb
Host smart-efd78dd7-6069-4386-9bdc-a4510e73e16c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123466807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1123466807
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1262369550
Short name T230
Test name
Test status
Simulation time 390164470 ps
CPU time 0.78 seconds
Started Aug 14 04:31:48 PM PDT 24
Finished Aug 14 04:31:49 PM PDT 24
Peak memory 192008 kb
Host smart-8ce271fb-fcd0-4d5e-9121-71503e8b5c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262369550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1262369550
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1435938096
Short name T206
Test name
Test status
Simulation time 56950969335 ps
CPU time 76.89 seconds
Started Aug 14 04:31:59 PM PDT 24
Finished Aug 14 04:33:15 PM PDT 24
Peak memory 192060 kb
Host smart-2a6c77a3-e4d1-4341-b64d-215ad2b13060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435938096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1435938096
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.204451998
Short name T269
Test name
Test status
Simulation time 574521060 ps
CPU time 1.06 seconds
Started Aug 14 04:31:48 PM PDT 24
Finished Aug 14 04:31:50 PM PDT 24
Peak memory 191996 kb
Host smart-17d397ee-b76c-4aa1-8ee9-80b4f94aa696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204451998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.204451998
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.3516266924
Short name T209
Test name
Test status
Simulation time 3371520342 ps
CPU time 11.05 seconds
Started Aug 14 04:32:11 PM PDT 24
Finished Aug 14 04:32:27 PM PDT 24
Peak memory 198712 kb
Host smart-82483c85-325b-4513-bd43-9ac47d6f8b78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516266924 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.3516266924
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.940557600
Short name T208
Test name
Test status
Simulation time 30756407280 ps
CPU time 12.89 seconds
Started Aug 14 04:32:08 PM PDT 24
Finished Aug 14 04:32:21 PM PDT 24
Peak memory 192056 kb
Host smart-10701ee6-67c1-49e4-9d62-d2f3db9f0270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940557600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.940557600
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.759669546
Short name T281
Test name
Test status
Simulation time 699148259 ps
CPU time 0.64 seconds
Started Aug 14 04:31:54 PM PDT 24
Finished Aug 14 04:31:55 PM PDT 24
Peak memory 196892 kb
Host smart-c2db83f7-bc8b-4b79-ade4-c63573c8a101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759669546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.759669546
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.411219406
Short name T263
Test name
Test status
Simulation time 7490195280 ps
CPU time 11.99 seconds
Started Aug 14 04:32:05 PM PDT 24
Finished Aug 14 04:32:17 PM PDT 24
Peak memory 197132 kb
Host smart-b559b1ac-a7a5-45ef-8966-fa4090f4c0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411219406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.411219406
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2955894217
Short name T201
Test name
Test status
Simulation time 514470504 ps
CPU time 0.99 seconds
Started Aug 14 04:32:06 PM PDT 24
Finished Aug 14 04:32:07 PM PDT 24
Peak memory 192032 kb
Host smart-4cec4750-b9e8-4fb2-91b4-711801c1c5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955894217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2955894217
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.493554277
Short name T271
Test name
Test status
Simulation time 60504945146 ps
CPU time 7.81 seconds
Started Aug 14 04:32:05 PM PDT 24
Finished Aug 14 04:32:13 PM PDT 24
Peak memory 192080 kb
Host smart-81a2ade8-007c-4848-a065-33de5cec183c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493554277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.493554277
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2227010965
Short name T218
Test name
Test status
Simulation time 496296792 ps
CPU time 0.83 seconds
Started Aug 14 04:31:50 PM PDT 24
Finished Aug 14 04:31:51 PM PDT 24
Peak memory 196788 kb
Host smart-188e800b-e89e-4816-ab88-1b3655673a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227010965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2227010965
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.4131682915
Short name T192
Test name
Test status
Simulation time 6045226979 ps
CPU time 16.01 seconds
Started Aug 14 04:31:56 PM PDT 24
Finished Aug 14 04:32:12 PM PDT 24
Peak memory 214076 kb
Host smart-a54e4dec-0795-4fe0-a662-935bc62838ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131682915 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.4131682915
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.4245870893
Short name T29
Test name
Test status
Simulation time 33475125429 ps
CPU time 5.69 seconds
Started Aug 14 04:32:07 PM PDT 24
Finished Aug 14 04:32:12 PM PDT 24
Peak memory 197044 kb
Host smart-35be34aa-6936-4a90-94ae-d8c743e82419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245870893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.4245870893
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3670285134
Short name T219
Test name
Test status
Simulation time 759699412 ps
CPU time 0.63 seconds
Started Aug 14 04:32:17 PM PDT 24
Finished Aug 14 04:32:18 PM PDT 24
Peak memory 196848 kb
Host smart-86314eaf-4c48-4e28-932a-9f310a294c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670285134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3670285134
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1984781822
Short name T228
Test name
Test status
Simulation time 25432442863 ps
CPU time 31.57 seconds
Started Aug 14 04:32:15 PM PDT 24
Finished Aug 14 04:32:47 PM PDT 24
Peak memory 192048 kb
Host smart-ffd5839f-2073-4f99-8ca6-4decf037984b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984781822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1984781822
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2537230639
Short name T212
Test name
Test status
Simulation time 513736150 ps
CPU time 0.65 seconds
Started Aug 14 04:32:13 PM PDT 24
Finished Aug 14 04:32:13 PM PDT 24
Peak memory 192036 kb
Host smart-1371f852-182b-4750-b3de-d7c9b47e405e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537230639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2537230639
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2720278039
Short name T213
Test name
Test status
Simulation time 15346225038 ps
CPU time 3.2 seconds
Started Aug 14 04:32:16 PM PDT 24
Finished Aug 14 04:32:19 PM PDT 24
Peak memory 192052 kb
Host smart-ece1bebb-61ed-4c99-aa57-08f29caee7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720278039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2720278039
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.4211993326
Short name T285
Test name
Test status
Simulation time 416623968 ps
CPU time 1.17 seconds
Started Aug 14 04:32:09 PM PDT 24
Finished Aug 14 04:32:10 PM PDT 24
Peak memory 196804 kb
Host smart-d9ec32fb-3168-458f-a80c-114e76818b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211993326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.4211993326
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.580116714
Short name T240
Test name
Test status
Simulation time 39322579453 ps
CPU time 13.65 seconds
Started Aug 14 04:32:09 PM PDT 24
Finished Aug 14 04:32:22 PM PDT 24
Peak memory 192032 kb
Host smart-1599ee20-8278-490a-9940-34b9e05360ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580116714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.580116714
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3667614941
Short name T268
Test name
Test status
Simulation time 538836803 ps
CPU time 1.31 seconds
Started Aug 14 04:32:09 PM PDT 24
Finished Aug 14 04:32:11 PM PDT 24
Peak memory 192004 kb
Host smart-a324a961-4724-4940-b494-2f80368b0863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667614941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3667614941
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1908135650
Short name T253
Test name
Test status
Simulation time 11861441967 ps
CPU time 17.05 seconds
Started Aug 14 04:32:20 PM PDT 24
Finished Aug 14 04:32:37 PM PDT 24
Peak memory 192068 kb
Host smart-342263c8-71d0-4fb2-92f0-d6ba77bcd9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908135650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1908135650
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.995260698
Short name T243
Test name
Test status
Simulation time 478912394 ps
CPU time 0.73 seconds
Started Aug 14 04:31:57 PM PDT 24
Finished Aug 14 04:31:58 PM PDT 24
Peak memory 192016 kb
Host smart-dcebcaa1-ab47-4556-9565-9ba0df62d4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995260698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.995260698
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1154038545
Short name T249
Test name
Test status
Simulation time 11299717185 ps
CPU time 5.22 seconds
Started Aug 14 04:32:09 PM PDT 24
Finished Aug 14 04:32:15 PM PDT 24
Peak memory 197132 kb
Host smart-975bc9b1-da37-475f-b619-146c578bc88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154038545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1154038545
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2564225122
Short name T241
Test name
Test status
Simulation time 550938698 ps
CPU time 1.35 seconds
Started Aug 14 04:32:12 PM PDT 24
Finished Aug 14 04:32:13 PM PDT 24
Peak memory 192000 kb
Host smart-792ddcd7-1767-4708-8cc4-12f1d821382f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564225122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2564225122
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2282337853
Short name T260
Test name
Test status
Simulation time 15341560888 ps
CPU time 11.44 seconds
Started Aug 14 04:31:32 PM PDT 24
Finished Aug 14 04:31:49 PM PDT 24
Peak memory 197044 kb
Host smart-89f75124-804c-4a89-a793-60bc48c4c599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282337853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2282337853
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3985584513
Short name T15
Test name
Test status
Simulation time 4369977126 ps
CPU time 2.22 seconds
Started Aug 14 04:32:02 PM PDT 24
Finished Aug 14 04:32:05 PM PDT 24
Peak memory 215992 kb
Host smart-93879afa-7b0e-4c17-a657-01d05c012719
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985584513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3985584513
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2834873389
Short name T265
Test name
Test status
Simulation time 506684429 ps
CPU time 0.98 seconds
Started Aug 14 04:31:36 PM PDT 24
Finished Aug 14 04:31:37 PM PDT 24
Peak memory 196820 kb
Host smart-589fd39c-a0c2-422f-ba23-64faebe301ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834873389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2834873389
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2216589768
Short name T248
Test name
Test status
Simulation time 50347409230 ps
CPU time 37.85 seconds
Started Aug 14 04:32:16 PM PDT 24
Finished Aug 14 04:32:59 PM PDT 24
Peak memory 192092 kb
Host smart-883a98d1-335d-4366-a6eb-647c50d87262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216589768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2216589768
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2084611420
Short name T215
Test name
Test status
Simulation time 459143442 ps
CPU time 1.15 seconds
Started Aug 14 04:32:18 PM PDT 24
Finished Aug 14 04:32:19 PM PDT 24
Peak memory 192016 kb
Host smart-170d6a48-3f03-4930-8838-4ea844db166a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084611420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2084611420
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2675211254
Short name T197
Test name
Test status
Simulation time 41021360396 ps
CPU time 58.87 seconds
Started Aug 14 04:32:25 PM PDT 24
Finished Aug 14 04:33:24 PM PDT 24
Peak memory 192092 kb
Host smart-41a4a917-05ff-45d4-bc59-0162e2aae575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675211254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2675211254
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2876143101
Short name T202
Test name
Test status
Simulation time 463792947 ps
CPU time 0.75 seconds
Started Aug 14 04:32:18 PM PDT 24
Finished Aug 14 04:32:19 PM PDT 24
Peak memory 192080 kb
Host smart-913759fb-bbc7-4747-99da-12406785853d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876143101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2876143101
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.432875437
Short name T224
Test name
Test status
Simulation time 12820255065 ps
CPU time 9.66 seconds
Started Aug 14 04:32:26 PM PDT 24
Finished Aug 14 04:32:36 PM PDT 24
Peak memory 192060 kb
Host smart-b48a4d56-23d4-4a7d-bc79-89f95d97b467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432875437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.432875437
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2331203510
Short name T283
Test name
Test status
Simulation time 407943709 ps
CPU time 0.75 seconds
Started Aug 14 04:32:23 PM PDT 24
Finished Aug 14 04:32:29 PM PDT 24
Peak memory 190880 kb
Host smart-db707d4f-9d8d-4b7a-a02f-8d7d70d3d354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331203510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2331203510
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2720051850
Short name T278
Test name
Test status
Simulation time 10348457932 ps
CPU time 4.07 seconds
Started Aug 14 04:32:28 PM PDT 24
Finished Aug 14 04:32:33 PM PDT 24
Peak memory 197088 kb
Host smart-bd29da17-814c-438e-9777-27a100d711b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720051850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2720051850
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.4265843422
Short name T225
Test name
Test status
Simulation time 566771410 ps
CPU time 0.8 seconds
Started Aug 14 04:32:14 PM PDT 24
Finished Aug 14 04:32:14 PM PDT 24
Peak memory 192012 kb
Host smart-4d982024-8c9e-4f88-9b5a-7964782430cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265843422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.4265843422
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3108000673
Short name T262
Test name
Test status
Simulation time 33085835193 ps
CPU time 21.79 seconds
Started Aug 14 04:32:08 PM PDT 24
Finished Aug 14 04:32:30 PM PDT 24
Peak memory 192032 kb
Host smart-3629a894-bbd5-40e1-b082-700ff4066227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108000673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3108000673
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2130597649
Short name T11
Test name
Test status
Simulation time 430966208 ps
CPU time 1.11 seconds
Started Aug 14 04:32:14 PM PDT 24
Finished Aug 14 04:32:15 PM PDT 24
Peak memory 196864 kb
Host smart-82193a89-937d-432e-a06f-7fa9807cecae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130597649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2130597649
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2754066151
Short name T257
Test name
Test status
Simulation time 12403856917 ps
CPU time 4.77 seconds
Started Aug 14 04:32:30 PM PDT 24
Finished Aug 14 04:32:35 PM PDT 24
Peak memory 197328 kb
Host smart-66018a7d-c290-4c07-b260-9e12b79524f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754066151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2754066151
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.4096747475
Short name T252
Test name
Test status
Simulation time 489240915 ps
CPU time 0.9 seconds
Started Aug 14 04:32:19 PM PDT 24
Finished Aug 14 04:32:20 PM PDT 24
Peak memory 192036 kb
Host smart-2739fb74-fb63-45e9-b95f-8e0670bf0fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096747475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.4096747475
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.506922078
Short name T226
Test name
Test status
Simulation time 13866707342 ps
CPU time 7.75 seconds
Started Aug 14 04:32:23 PM PDT 24
Finished Aug 14 04:32:30 PM PDT 24
Peak memory 192080 kb
Host smart-8e54daac-1c1b-4503-91c7-a7724fba2da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506922078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.506922078
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2410963657
Short name T221
Test name
Test status
Simulation time 495491800 ps
CPU time 0.72 seconds
Started Aug 14 04:32:26 PM PDT 24
Finished Aug 14 04:32:27 PM PDT 24
Peak memory 196860 kb
Host smart-9dd45a14-03f1-47cc-8d8a-52be9b51bfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410963657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2410963657
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3507472910
Short name T203
Test name
Test status
Simulation time 52320348105 ps
CPU time 6.93 seconds
Started Aug 14 04:32:17 PM PDT 24
Finished Aug 14 04:32:24 PM PDT 24
Peak memory 192080 kb
Host smart-21079c5a-6c8c-44a8-9ae3-e87998f08376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507472910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3507472910
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2344173589
Short name T7
Test name
Test status
Simulation time 536887863 ps
CPU time 0.93 seconds
Started Aug 14 04:32:29 PM PDT 24
Finished Aug 14 04:32:31 PM PDT 24
Peak memory 191964 kb
Host smart-ee219fe0-88fd-4d49-bb3e-4f944e17c806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344173589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2344173589
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1871677904
Short name T275
Test name
Test status
Simulation time 28774614379 ps
CPU time 21.76 seconds
Started Aug 14 04:32:59 PM PDT 24
Finished Aug 14 04:33:21 PM PDT 24
Peak memory 192064 kb
Host smart-c08e0da4-f90e-4c1b-a18c-93346c353e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871677904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1871677904
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1643089630
Short name T234
Test name
Test status
Simulation time 568715808 ps
CPU time 0.66 seconds
Started Aug 14 04:32:13 PM PDT 24
Finished Aug 14 04:32:14 PM PDT 24
Peak memory 192024 kb
Host smart-c4b99188-d8e6-4911-8507-c9f53c15217d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643089630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1643089630
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2667721664
Short name T276
Test name
Test status
Simulation time 25758043342 ps
CPU time 34.35 seconds
Started Aug 14 04:32:28 PM PDT 24
Finished Aug 14 04:33:02 PM PDT 24
Peak memory 192124 kb
Host smart-8f682dc9-01c4-4413-bed0-b2be45f7ace2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667721664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2667721664
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1039458757
Short name T254
Test name
Test status
Simulation time 429094439 ps
CPU time 0.73 seconds
Started Aug 14 04:32:22 PM PDT 24
Finished Aug 14 04:32:23 PM PDT 24
Peak memory 192016 kb
Host smart-1dfd83cd-2b3b-4bfc-9d78-f381d834f810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039458757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1039458757
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.675299598
Short name T191
Test name
Test status
Simulation time 663466541 ps
CPU time 0.8 seconds
Started Aug 14 04:31:30 PM PDT 24
Finished Aug 14 04:31:31 PM PDT 24
Peak memory 192012 kb
Host smart-55a5c362-99e7-416b-9e08-d8b4547d2fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675299598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.675299598
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3257362646
Short name T280
Test name
Test status
Simulation time 456709136 ps
CPU time 0.91 seconds
Started Aug 14 04:31:23 PM PDT 24
Finished Aug 14 04:31:24 PM PDT 24
Peak memory 196808 kb
Host smart-26800488-6620-4658-abbe-5e10da795c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257362646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3257362646
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3321892462
Short name T196
Test name
Test status
Simulation time 50402889298 ps
CPU time 20.05 seconds
Started Aug 14 04:31:38 PM PDT 24
Finished Aug 14 04:31:58 PM PDT 24
Peak memory 192080 kb
Host smart-59821058-5a67-4b97-8e76-53f53427b50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321892462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3321892462
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.684578739
Short name T236
Test name
Test status
Simulation time 615844289 ps
CPU time 0.64 seconds
Started Aug 14 04:31:39 PM PDT 24
Finished Aug 14 04:31:40 PM PDT 24
Peak memory 196816 kb
Host smart-06279701-d986-4330-8806-f44e8d26f084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684578739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.684578739
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.74315045
Short name T210
Test name
Test status
Simulation time 30902382531 ps
CPU time 43.68 seconds
Started Aug 14 04:31:26 PM PDT 24
Finished Aug 14 04:32:10 PM PDT 24
Peak memory 197076 kb
Host smart-4ad2addc-103f-455c-ac4f-0daddf5d7950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74315045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.74315045
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.600858115
Short name T232
Test name
Test status
Simulation time 579980668 ps
CPU time 1.31 seconds
Started Aug 14 04:31:38 PM PDT 24
Finished Aug 14 04:31:40 PM PDT 24
Peak memory 196844 kb
Host smart-40c543e2-aebb-4aaa-92ef-983862b442ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600858115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.600858115
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.4099685262
Short name T235
Test name
Test status
Simulation time 13562812308 ps
CPU time 5.56 seconds
Started Aug 14 04:31:40 PM PDT 24
Finished Aug 14 04:31:45 PM PDT 24
Peak memory 192064 kb
Host smart-6bd963a9-77e2-4a13-a6dd-ff3dd1579038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099685262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.4099685262
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.651441807
Short name T199
Test name
Test status
Simulation time 430747121 ps
CPU time 0.73 seconds
Started Aug 14 04:31:25 PM PDT 24
Finished Aug 14 04:31:26 PM PDT 24
Peak memory 192012 kb
Host smart-44db5b65-99ac-4ad4-879d-272b34260158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651441807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.651441807
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1059217557
Short name T255
Test name
Test status
Simulation time 15851824229 ps
CPU time 20.24 seconds
Started Aug 14 04:31:33 PM PDT 24
Finished Aug 14 04:31:53 PM PDT 24
Peak memory 192088 kb
Host smart-e1a562de-4d5e-4ba4-b037-9b4cb18fd674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059217557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1059217557
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3554608565
Short name T256
Test name
Test status
Simulation time 476062262 ps
CPU time 1.34 seconds
Started Aug 14 04:31:38 PM PDT 24
Finished Aug 14 04:31:39 PM PDT 24
Peak memory 192016 kb
Host smart-7953c7a6-cad8-44ca-8f3d-dca3a22fe5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554608565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3554608565
Directory /workspace/9.aon_timer_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%