Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39874	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	295679	1		T1	14		T2	2130		T3	184

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	85565	1		T1	1		T2	667		T3	34
values[0x0]	118348	1		T1	10		T2	793		T3	122
values[0x1]	131640	1		T1	9		T2	927		T3	118

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24558	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	310995	1		T1	14		T2	2254		T3	201

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1139	1		T2	79		T9	4		T15	122
valid_sources[0x01]	1214	1		T9	8		T36	53		T43	33
valid_sources[0x02]	1429	1		T2	1		T4	1		T9	8
valid_sources[0x03]	1217	1		T9	30		T15	155		T36	47
valid_sources[0x04]	1267	1		T2	4		T3	6		T9	29
valid_sources[0x05]	1266	1		T2	69		T3	1		T9	30
valid_sources[0x06]	1393	1		T3	2		T9	28		T15	162
valid_sources[0x07]	1136	1		T2	5		T9	22		T15	9
valid_sources[0x08]	1507	1		T9	16		T15	10		T33	5
valid_sources[0x09]	1099	1		T9	29		T15	2		T33	1
valid_sources[0x0a]	1083	1		T9	21		T15	2		T36	53
valid_sources[0x0b]	1381	1		T2	106		T9	19		T13	1
valid_sources[0x0c]	1291	1		T2	1		T3	7		T9	13
valid_sources[0x0d]	989	1		T3	4		T9	13		T15	12
valid_sources[0x0e]	1516	1		T2	1		T9	11		T15	2
valid_sources[0x0f]	1067	1		T3	3		T9	16		T15	2
valid_sources[0x10]	1011	1		T2	1		T3	1		T9	11
valid_sources[0x11]	1007	1		T9	26		T15	3		T50	3
valid_sources[0x12]	955	1		T2	1		T9	23		T10	3
valid_sources[0x13]	1217	1		T9	28		T33	2		T36	45
valid_sources[0x14]	1304	1		T2	2		T3	7		T9	13
valid_sources[0x15]	1001	1		T9	9		T15	3		T33	2
valid_sources[0x16]	1385	1		T2	55		T9	15		T15	8
valid_sources[0x17]	1862	1		T9	14		T15	185		T33	2
valid_sources[0x18]	2070	1		T2	7		T9	9		T15	80
valid_sources[0x19]	1240	1		T9	8		T15	1		T33	2
valid_sources[0x1a]	1213	1		T9	15		T11	7		T33	1
valid_sources[0x1b]	1199	1		T2	2		T9	25		T15	12
valid_sources[0x1c]	1108	1		T9	11		T36	48		T43	30
valid_sources[0x1d]	1307	1		T9	20		T15	82		T33	1
valid_sources[0x1e]	1564	1		T2	174		T3	6		T9	19
valid_sources[0x1f]	1221	1		T2	1		T4	7		T9	13
valid_sources[0x20]	1461	1		T3	1		T4	1		T9	17
valid_sources[0x21]	941	1		T9	12		T15	9		T36	49
valid_sources[0x22]	991	1		T2	2		T7	1		T9	29
valid_sources[0x23]	1758	1		T9	22		T15	2		T31	9
valid_sources[0x24]	1415	1		T2	1		T4	1		T9	32
valid_sources[0x25]	1009	1		T2	4		T3	2		T9	14
valid_sources[0x26]	1214	1		T9	7		T13	1		T33	3
valid_sources[0x27]	1354	1		T2	87		T3	2		T4	2
valid_sources[0x28]	1341	1		T3	5		T9	23		T15	1
valid_sources[0x29]	1405	1		T2	1		T3	2		T9	21
valid_sources[0x2a]	1046	1		T2	4		T9	18		T15	3
valid_sources[0x2b]	1488	1		T2	3		T9	22		T15	1
valid_sources[0x2c]	1113	1		T9	11		T33	1		T36	48
valid_sources[0x2d]	1563	1		T2	18		T3	5		T4	1
valid_sources[0x2e]	1199	1		T3	1		T9	23		T15	103
valid_sources[0x2f]	1047	1		T2	1		T9	17		T15	10
valid_sources[0x30]	1082	1		T2	1		T3	3		T9	22
valid_sources[0x31]	1755	1		T9	23		T15	217		T36	48
valid_sources[0x32]	1568	1		T2	14		T4	5		T9	7
valid_sources[0x33]	1223	1		T9	24		T15	3		T33	2
valid_sources[0x34]	1235	1		T9	10		T15	139		T33	4
valid_sources[0x35]	1310	1		T2	5		T3	5		T9	34
valid_sources[0x36]	1218	1		T2	11		T4	7		T9	6
valid_sources[0x37]	1218	1		T2	35		T3	3		T9	22
valid_sources[0x38]	1366	1		T9	20		T15	19		T36	39
valid_sources[0x39]	1048	1		T2	61		T9	13		T15	2
valid_sources[0x3a]	1584	1		T2	2		T4	2		T9	22
valid_sources[0x3b]	1201	1		T3	1		T9	17		T13	1
valid_sources[0x3c]	1224	1		T9	12		T15	3		T32	1
valid_sources[0x3d]	1042	1		T9	23		T15	1		T33	1
valid_sources[0x3e]	1406	1		T2	3		T9	17		T15	16
valid_sources[0x3f]	1067	1		T2	2		T4	3		T7	3
valid_sources[0x40]	1291	1		T9	19		T15	6		T33	2
valid_sources[0x41]	896	1		T4	9		T9	19		T33	3
valid_sources[0x42]	1404	1		T9	9		T15	134		T36	57
valid_sources[0x43]	1235	1		T3	8		T9	15		T33	1
valid_sources[0x44]	1322	1		T2	2		T3	1		T9	23
valid_sources[0x45]	1427	1		T9	10		T10	1		T15	94
valid_sources[0x46]	900	1		T9	11		T33	2		T36	54
valid_sources[0x47]	1722	1		T6	18		T7	1		T9	13
valid_sources[0x48]	1400	1		T5	22		T9	11		T36	33
valid_sources[0x49]	1322	1		T2	61		T3	1		T9	15
valid_sources[0x4a]	1370	1		T2	1		T3	2		T9	17
valid_sources[0x4b]	1106	1		T2	23		T3	1		T9	31
valid_sources[0x4c]	1322	1		T3	2		T9	22		T15	239
valid_sources[0x4d]	1160	1		T2	1		T3	5		T9	21
valid_sources[0x4e]	1384	1		T2	86		T3	2		T4	11
valid_sources[0x4f]	1242	1		T9	23		T15	1		T33	3
valid_sources[0x50]	1571	1		T1	16		T2	74		T3	1
valid_sources[0x51]	1319	1		T2	1		T9	20		T33	2
valid_sources[0x52]	1553	1		T3	3		T4	3		T9	22
valid_sources[0x53]	1592	1		T3	2		T9	9		T15	4
valid_sources[0x54]	1190	1		T2	1		T9	13		T15	127
valid_sources[0x55]	1602	1		T3	1		T4	11		T9	14
valid_sources[0x56]	933	1		T2	2		T9	18		T15	3
valid_sources[0x57]	1294	1		T9	13		T33	1		T36	55
valid_sources[0x58]	1774	1		T3	3		T9	19		T33	2
valid_sources[0x59]	1059	1		T9	19		T15	2		T33	2
valid_sources[0x5a]	1277	1		T9	12		T15	4		T33	1
valid_sources[0x5b]	1700	1		T3	2		T9	16		T15	1
valid_sources[0x5c]	1044	1		T4	4		T9	17		T15	1
valid_sources[0x5d]	1641	1		T2	6		T4	2		T9	12
valid_sources[0x5e]	1587	1		T4	33		T9	17		T15	3
valid_sources[0x5f]	1044	1		T9	18		T10	2		T15	3
valid_sources[0x60]	1147	1		T2	2		T3	6		T9	15
valid_sources[0x61]	1574	1		T3	4		T9	6		T11	1
valid_sources[0x62]	1330	1		T2	1		T9	13		T15	252
valid_sources[0x63]	1409	1		T2	4		T4	14		T9	8
valid_sources[0x64]	1596	1		T2	108		T3	3		T9	17
valid_sources[0x65]	1153	1		T9	21		T11	2		T15	1
valid_sources[0x66]	1369	1		T9	16		T15	11		T33	1
valid_sources[0x67]	1223	1		T3	6		T9	7		T15	3
valid_sources[0x68]	1054	1		T9	10		T15	32		T33	2
valid_sources[0x69]	1315	1		T2	1		T9	13		T31	4
valid_sources[0x6a]	1438	1		T3	1		T9	38		T33	2
valid_sources[0x6b]	1022	1		T2	5		T9	13		T36	40
valid_sources[0x6c]	1564	1		T2	1		T3	2		T9	18
valid_sources[0x6d]	1953	1		T3	5		T9	16		T33	2
valid_sources[0x6e]	1286	1		T3	3		T9	15		T15	6
valid_sources[0x6f]	966	1		T2	1		T9	17		T15	56
valid_sources[0x70]	1040	1		T2	16		T9	17		T15	1
valid_sources[0x71]	1278	1		T3	3		T4	10		T9	16
valid_sources[0x72]	1890	1		T3	1		T4	2		T9	24
valid_sources[0x73]	1276	1		T3	1		T9	18		T15	1
valid_sources[0x74]	997	1		T3	1		T4	2		T9	18
valid_sources[0x75]	1036	1		T4	2		T9	27		T15	8
valid_sources[0x76]	1289	1		T2	104		T3	5		T9	15
valid_sources[0x77]	1139	1		T9	15		T15	2		T32	1
valid_sources[0x78]	999	1		T2	20		T4	9		T9	18
valid_sources[0x79]	1209	1		T9	15		T33	1		T36	43
valid_sources[0x7a]	1299	1		T2	1		T3	8		T7	1
valid_sources[0x7b]	1165	1		T3	5		T9	19		T13	1
valid_sources[0x7c]	1537	1		T2	7		T9	16		T15	1
valid_sources[0x7d]	1303	1		T3	2		T9	18		T33	2
valid_sources[0x7e]	1555	1		T2	4		T3	5		T9	15
valid_sources[0x7f]	1156	1		T4	4		T9	21		T15	1
valid_sources[0x80]	1212	1		T3	4		T9	16		T33	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

73287

1

T1

1

T2

587

T3

22

values[0x0]

all_enables

biggest_size

111294

1

T1

7

T2

764

T3

83

values[0x1]

all_enables

biggest_size

111098

1

T1

6

T2

779

T3

79