Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	630095135	283767	0	0
wdog_bark_thold_rd_A	630095135	7781	0	0
wdog_bite_thold_rd_A	630095135	7174	0	0
wdog_ctrl_rd_A	630095135	7402	0	0
wdog_regwen_rd_A	630095135	7945	0	0
wkup_ctrl_rd_A	630095135	7046	0	0
wkup_thold_hi_rd_A	630095135	7949	0	0
wkup_thold_lo_rd_A	630095135	7145	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630095135	283767	0	0
T2	127456	3244	0	0
T3	197510	0	0	0
T4	187806	0	0	0
T5	52490	0	0	0
T6	47017	0	0	0
T7	28707	0	0	0
T8	206331	0	0	0
T9	269238	3806	0	0
T10	199076	0	0	0
T11	14804	0	0	0
T15	0	8516	0	0
T36	0	11300	0	0
T43	0	4066	0	0
T44	0	14889	0	0
T45	0	6126	0	0
T46	0	3262	0	0
T47	0	6377	0	0
T48	0	6085	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630095135	7781	0	0
T9	269238	446	0	0
T10	199076	0	0	0
T11	14804	0	0	0
T12	435732	0	0	0
T13	344888	0	0	0
T14	5792	0	0	0
T15	280172	0	0	0
T30	33417	0	0	0
T31	36469	0	0	0
T32	17079	0	0	0
T47	0	605	0	0
T75	0	308	0	0
T76	0	1187	0	0
T77	0	773	0	0
T78	0	349	0	0
T79	0	308	0	0
T80	0	601	0	0
T81	0	623	0	0
T82	0	243	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630095135	7174	0	0
T9	269238	418	0	0
T10	199076	0	0	0
T11	14804	0	0	0
T12	435732	0	0	0
T13	344888	0	0	0
T14	5792	0	0	0
T15	280172	0	0	0
T30	33417	0	0	0
T31	36469	0	0	0
T32	17079	0	0	0
T47	0	687	0	0
T75	0	369	0	0
T76	0	971	0	0
T77	0	661	0	0
T78	0	270	0	0
T79	0	241	0	0
T80	0	511	0	0
T81	0	625	0	0
T82	0	203	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630095135	7402	0	0
T9	269238	345	0	0
T10	199076	0	0	0
T11	14804	0	0	0
T12	435732	0	0	0
T13	344888	0	0	0
T14	5792	0	0	0
T15	280172	0	0	0
T30	33417	0	0	0
T31	36469	0	0	0
T32	17079	0	0	0
T47	0	600	0	0
T75	0	377	0	0
T76	0	913	0	0
T77	0	666	0	0
T78	0	288	0	0
T79	0	318	0	0
T80	0	584	0	0
T81	0	593	0	0
T82	0	203	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630095135	7945	0	0
T9	269238	529	0	0
T10	199076	0	0	0
T11	14804	0	0	0
T12	435732	0	0	0
T13	344888	0	0	0
T14	5792	0	0	0
T15	280172	0	0	0
T30	33417	0	0	0
T31	36469	0	0	0
T32	17079	0	0	0
T47	0	616	0	0
T75	0	303	0	0
T76	0	1043	0	0
T77	0	660	0	0
T78	0	313	0	0
T79	0	266	0	0
T80	0	601	0	0
T81	0	651	0	0
T82	0	224	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630095135	7046	0	0
T9	269238	417	0	0
T10	199076	0	0	0
T11	14804	0	0	0
T12	435732	0	0	0
T13	344888	0	0	0
T14	5792	0	0	0
T15	280172	0	0	0
T30	33417	0	0	0
T31	36469	0	0	0
T32	17079	0	0	0
T47	0	588	0	0
T75	0	274	0	0
T76	0	914	0	0
T77	0	703	0	0
T78	0	236	0	0
T79	0	285	0	0
T80	0	517	0	0
T81	0	592	0	0
T82	0	195	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630095135	7949	0	0
T9	269238	618	0	0
T10	199076	0	0	0
T11	14804	0	0	0
T12	435732	0	0	0
T13	344888	0	0	0
T14	5792	0	0	0
T15	280172	0	0	0
T30	33417	0	0	0
T31	36469	0	0	0
T32	17079	0	0	0
T47	0	732	0	0
T75	0	355	0	0
T76	0	970	0	0
T77	0	740	0	0
T78	0	315	0	0
T79	0	245	0	0
T80	0	609	0	0
T81	0	533	0	0
T82	0	149	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	630095135	7145	0	0
T9	269238	490	0	0
T10	199076	0	0	0
T11	14804	0	0	0
T12	435732	0	0	0
T13	344888	0	0	0
T14	5792	0	0	0
T15	280172	0	0	0
T30	33417	0	0	0
T31	36469	0	0	0
T32	17079	0	0	0
T47	0	564	0	0
T75	0	370	0	0
T76	0	948	0	0
T77	0	656	0	0
T78	0	284	0	0
T79	0	280	0	0
T80	0	550	0	0
T81	0	553	0	0
T82	0	213	0	0