Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45441	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

341970

1

T1

13

T2

260

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	97471	1			T1	1		T2	39		T3	1
values[0x0]	137349	1			T1	7		T2	197		T3	9
values[0x1]	152591	1			T1	12		T2	134		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27138	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

360273

1

T1

16

T2

284

T3

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1448	1			T9	2		T10	12		T12	26
valid_sources[0x01]	1342	1			T4	1		T9	2		T10	32
valid_sources[0x02]	1413	1			T4	2		T9	1		T10	19
valid_sources[0x03]	1280	1			T4	1		T10	25		T48	1
valid_sources[0x04]	1188	1			T3	1		T5	1		T6	2
valid_sources[0x05]	1269	1			T9	1		T10	39		T48	1
valid_sources[0x06]	1418	1			T5	1		T9	1		T10	21
valid_sources[0x07]	1373	1			T3	1		T4	7		T9	2
valid_sources[0x08]	1581	1			T4	69		T5	3		T9	1
valid_sources[0x09]	2093	1			T4	208		T5	3		T10	18
valid_sources[0x0a]	1330	1			T5	2		T10	33		T12	32
valid_sources[0x0b]	1483	1			T4	23		T5	1		T9	2
valid_sources[0x0c]	1503	1			T4	7		T9	1		T10	19
valid_sources[0x0d]	1476	1			T4	28		T5	1		T9	4
valid_sources[0x0e]	1373	1			T4	1		T5	6		T9	2
valid_sources[0x0f]	1174	1			T4	1		T5	1		T9	2
valid_sources[0x10]	1447	1			T4	3		T9	2		T10	14
valid_sources[0x11]	1731	1			T4	27		T10	27		T12	33
valid_sources[0x12]	1385	1			T9	1		T10	29		T12	40
valid_sources[0x13]	1577	1			T4	96		T6	1		T9	5
valid_sources[0x14]	2123	1			T4	175		T9	1		T10	23
valid_sources[0x15]	1983	1			T4	3		T5	1		T9	2
valid_sources[0x16]	1454	1			T4	13		T5	2		T10	40
valid_sources[0x17]	1765	1			T4	101		T5	7		T9	2
valid_sources[0x18]	1385	1			T4	2		T5	3		T9	1
valid_sources[0x19]	1616	1			T4	1		T10	8		T48	1
valid_sources[0x1a]	1793	1			T3	3		T4	1		T9	1
valid_sources[0x1b]	1827	1			T5	1		T9	1		T10	23
valid_sources[0x1c]	1400	1			T4	39		T5	24		T9	3
valid_sources[0x1d]	1598	1			T4	1		T9	2		T10	25
valid_sources[0x1e]	1657	1			T4	3		T9	1		T10	17
valid_sources[0x1f]	1258	1			T4	2		T5	6		T10	15
valid_sources[0x20]	1705	1			T3	1		T9	1		T10	29
valid_sources[0x21]	1588	1			T4	3		T5	1		T10	25
valid_sources[0x22]	1960	1			T4	35		T5	12		T6	2
valid_sources[0x23]	1475	1			T3	1		T4	41		T5	2
valid_sources[0x24]	2519	1			T4	2		T9	1		T10	9
valid_sources[0x25]	1144	1			T4	5		T9	1		T10	33
valid_sources[0x26]	1136	1			T4	6		T5	1		T9	1
valid_sources[0x27]	1435	1			T4	167		T9	3		T10	26
valid_sources[0x28]	1368	1			T4	4		T9	1		T10	34
valid_sources[0x29]	1390	1			T4	2		T5	3		T10	14
valid_sources[0x2a]	1372	1			T3	1		T4	1		T9	1
valid_sources[0x2b]	2116	1			T4	150		T5	5		T10	30
valid_sources[0x2c]	1294	1			T4	3		T9	3		T10	12
valid_sources[0x2d]	1492	1			T4	2		T5	2		T7	1
valid_sources[0x2e]	1314	1			T4	1		T9	2		T10	13
valid_sources[0x2f]	1573	1			T4	77		T9	2		T10	28
valid_sources[0x30]	1139	1			T4	4		T9	1		T10	28
valid_sources[0x31]	1516	1			T5	5		T9	1		T10	28
valid_sources[0x32]	1683	1			T3	1		T4	257		T5	4
valid_sources[0x33]	1390	1			T4	59		T10	23		T208	1
valid_sources[0x34]	1590	1			T4	91		T5	1		T9	1
valid_sources[0x35]	1763	1			T10	20		T41	1		T12	18
valid_sources[0x36]	2403	1			T4	2		T10	6		T12	21
valid_sources[0x37]	2139	1			T4	2		T5	1		T9	1
valid_sources[0x38]	1330	1			T4	88		T9	2		T10	30
valid_sources[0x39]	1946	1			T2	370		T4	10		T10	22
valid_sources[0x3a]	1612	1			T4	16		T5	2		T10	22
valid_sources[0x3b]	1564	1			T4	91		T9	1		T10	20
valid_sources[0x3c]	1289	1			T5	3		T9	3		T10	7
valid_sources[0x3d]	1715	1			T4	2		T9	1		T10	14
valid_sources[0x3e]	1197	1			T4	47		T9	4		T10	18
valid_sources[0x3f]	1048	1			T4	2		T5	2		T9	2
valid_sources[0x40]	1097	1			T4	4		T9	1		T10	29
valid_sources[0x41]	1264	1			T4	1		T5	1		T10	19
valid_sources[0x42]	1064	1			T4	5		T5	2		T7	1
valid_sources[0x43]	1479	1			T4	3		T10	11		T12	34
valid_sources[0x44]	1904	1			T4	19		T5	1		T9	2
valid_sources[0x45]	1537	1			T4	69		T9	1		T10	31
valid_sources[0x46]	1519	1			T9	1		T10	10		T12	19
valid_sources[0x47]	1624	1			T10	20		T12	34		T29	7
valid_sources[0x48]	1579	1			T4	2		T9	1		T10	16
valid_sources[0x49]	2016	1			T4	12		T9	1		T10	17
valid_sources[0x4a]	1366	1			T4	3		T9	1		T10	21
valid_sources[0x4b]	1551	1			T10	29		T164	4		T12	19
valid_sources[0x4c]	1325	1			T5	2		T10	13		T12	38
valid_sources[0x4d]	1876	1			T5	1		T7	1		T9	2
valid_sources[0x4e]	1431	1			T4	1		T10	35		T12	43
valid_sources[0x4f]	1462	1			T4	2		T9	1		T10	23
valid_sources[0x50]	1603	1			T4	7		T9	1		T10	26
valid_sources[0x51]	1530	1			T4	1		T5	9		T9	1
valid_sources[0x52]	1957	1			T7	1		T9	2		T10	22
valid_sources[0x53]	1665	1			T4	33		T7	1		T9	1
valid_sources[0x54]	2248	1			T4	291		T9	1		T10	34
valid_sources[0x55]	1260	1			T5	5		T9	2		T10	5
valid_sources[0x56]	1293	1			T4	7		T9	2		T10	16
valid_sources[0x57]	1297	1			T4	1		T9	1		T10	16
valid_sources[0x58]	1835	1			T4	106		T5	2		T9	4
valid_sources[0x59]	1530	1			T4	269		T5	2		T10	22
valid_sources[0x5a]	1547	1			T4	148		T9	3		T10	42
valid_sources[0x5b]	1575	1			T4	4		T7	1		T9	2
valid_sources[0x5c]	1806	1			T9	1		T10	37		T12	32
valid_sources[0x5d]	1328	1			T4	5		T5	3		T9	1
valid_sources[0x5e]	1487	1			T9	1		T10	16		T200	2
valid_sources[0x5f]	1841	1			T4	1		T10	11		T12	50
valid_sources[0x60]	1610	1			T4	3		T9	1		T10	18
valid_sources[0x61]	1699	1			T4	163		T5	3		T9	1
valid_sources[0x62]	1288	1			T4	4		T9	1		T10	39
valid_sources[0x63]	1551	1			T4	1		T10	13		T12	46
valid_sources[0x64]	1433	1			T4	134		T5	2		T10	22
valid_sources[0x65]	1960	1			T4	1		T10	25		T48	2
valid_sources[0x66]	1499	1			T4	176		T5	2		T10	14
valid_sources[0x67]	1444	1			T4	3		T9	1		T10	12
valid_sources[0x68]	1868	1			T4	4		T9	1		T10	31
valid_sources[0x69]	1256	1			T4	14		T9	3		T10	28
valid_sources[0x6a]	1511	1			T9	3		T10	22		T12	23
valid_sources[0x6b]	1562	1			T3	1		T4	38		T5	3
valid_sources[0x6c]	1628	1			T4	1		T10	12		T27	1
valid_sources[0x6d]	1407	1			T4	1		T9	2		T10	36
valid_sources[0x6e]	1608	1			T1	20		T4	87		T5	9
valid_sources[0x6f]	1480	1			T4	63		T5	2		T10	32
valid_sources[0x70]	1216	1			T3	1		T4	11		T10	18
valid_sources[0x71]	1903	1			T4	89		T9	1		T10	34
valid_sources[0x72]	1300	1			T4	3		T9	3		T10	23
valid_sources[0x73]	1322	1			T9	1		T10	11		T12	36
valid_sources[0x74]	1786	1			T4	204		T10	26		T12	10
valid_sources[0x75]	1458	1			T4	1		T5	6		T8	20
valid_sources[0x76]	1993	1			T4	2		T10	16		T12	10
valid_sources[0x77]	1370	1			T4	1		T5	2		T10	19
valid_sources[0x78]	1932	1			T9	2		T10	18		T12	31
valid_sources[0x79]	1224	1			T4	4		T9	1		T10	19
valid_sources[0x7a]	1774	1			T4	1		T7	1		T10	13
valid_sources[0x7b]	1337	1			T9	4		T10	37		T212	5
valid_sources[0x7c]	1332	1			T4	1		T5	4		T10	12
valid_sources[0x7d]	1901	1			T4	130		T9	1		T10	25
valid_sources[0x7e]	1316	1			T9	3		T10	21		T12	37
valid_sources[0x7f]	1317	1			T4	4		T5	2		T9	1
valid_sources[0x80]	1852	1			T4	3		T5	1		T10	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

83975

1

T2

20

T4

1472

T5

23

values[0x0]

all_enables

biggest_size

129580

1

T1

5

T2

140

T3

8

values[0x1]

all_enables

biggest_size

128415

1

T1

8

T2

100

T3

3