Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41153	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

299836

1

T1

215

T2

14

T3

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	86962	1			T1	41		T2	1		T3	1
values[0x0]	120791	1			T1	122		T2	7		T3	11
values[0x1]	133236	1			T1	137		T2	11		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25307	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

315682

1

T1

233

T2

15

T3

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1118	1			T2	1		T12	6		T13	41
valid_sources[0x01]	1839	1			T11	2		T12	25		T13	29
valid_sources[0x02]	1429	1			T11	2		T12	9		T13	21
valid_sources[0x03]	1370	1			T2	2		T12	16		T13	23
valid_sources[0x04]	1319	1			T12	9		T13	20		T14	28
valid_sources[0x05]	1189	1			T12	8		T13	26		T14	31
valid_sources[0x06]	2030	1			T11	3		T12	13		T13	27
valid_sources[0x07]	1436	1			T2	1		T11	10		T12	5
valid_sources[0x08]	1209	1			T10	6		T12	11		T13	25
valid_sources[0x09]	1069	1			T2	1		T12	15		T13	25
valid_sources[0x0a]	1474	1			T8	1		T12	8		T13	23
valid_sources[0x0b]	1655	1			T12	18		T13	24		T14	11
valid_sources[0x0c]	1306	1			T12	7		T13	20		T14	26
valid_sources[0x0d]	1123	1			T12	8		T13	29		T14	30
valid_sources[0x0e]	1385	1			T12	8		T13	25		T14	30
valid_sources[0x0f]	1412	1			T11	9		T12	15		T13	27
valid_sources[0x10]	1357	1			T12	17		T13	30		T14	29
valid_sources[0x11]	1201	1			T12	15		T13	25		T14	33
valid_sources[0x12]	1263	1			T10	5		T12	7		T13	37
valid_sources[0x13]	1411	1			T12	19		T13	14		T14	34
valid_sources[0x14]	1137	1			T12	12		T13	19		T14	33
valid_sources[0x15]	1232	1			T11	3		T12	12		T13	39
valid_sources[0x16]	1067	1			T7	1		T12	7		T13	23
valid_sources[0x17]	1503	1			T10	3		T12	21		T13	26
valid_sources[0x18]	950	1			T12	6		T13	26		T14	25
valid_sources[0x19]	1365	1			T6	1		T7	1		T12	9
valid_sources[0x1a]	1339	1			T12	16		T13	19		T14	19
valid_sources[0x1b]	1281	1			T12	12		T13	27		T14	33
valid_sources[0x1c]	1134	1			T12	15		T13	26		T14	22
valid_sources[0x1d]	1162	1			T12	14		T13	21		T14	31
valid_sources[0x1e]	1104	1			T2	1		T11	5		T12	16
valid_sources[0x1f]	1430	1			T12	11		T13	29		T14	23
valid_sources[0x20]	1461	1			T12	13		T13	21		T14	28
valid_sources[0x21]	1296	1			T6	1		T12	10		T13	26
valid_sources[0x22]	1105	1			T6	1		T11	19		T12	10
valid_sources[0x23]	1187	1			T12	6		T13	21		T14	33
valid_sources[0x24]	1379	1			T9	1		T10	20		T12	9
valid_sources[0x25]	1205	1			T11	1		T12	17		T13	23
valid_sources[0x26]	1065	1			T5	1		T12	13		T13	30
valid_sources[0x27]	1595	1			T11	2		T12	9		T13	13
valid_sources[0x28]	1232	1			T5	3		T6	1		T12	10
valid_sources[0x29]	1737	1			T12	7		T13	32		T14	38
valid_sources[0x2a]	1238	1			T4	4		T12	16		T13	17
valid_sources[0x2b]	1499	1			T11	4		T12	9		T13	36
valid_sources[0x2c]	1219	1			T12	7		T13	21		T14	20
valid_sources[0x2d]	1467	1			T12	12		T13	16		T14	32
valid_sources[0x2e]	1506	1			T11	5		T12	8		T13	14
valid_sources[0x2f]	1120	1			T12	13		T13	25		T14	22
valid_sources[0x30]	1241	1			T7	1		T9	1		T12	19
valid_sources[0x31]	1224	1			T11	9		T12	13		T13	40
valid_sources[0x32]	1035	1			T11	1		T12	16		T13	16
valid_sources[0x33]	1195	1			T11	5		T12	5		T13	28
valid_sources[0x34]	1314	1			T12	6		T13	19		T14	22
valid_sources[0x35]	1097	1			T12	18		T13	22		T14	23
valid_sources[0x36]	1134	1			T6	1		T11	2		T12	12
valid_sources[0x37]	1141	1			T5	1		T12	4		T13	25
valid_sources[0x38]	1461	1			T8	1		T11	4		T12	11
valid_sources[0x39]	1246	1			T12	12		T13	14		T14	29
valid_sources[0x3a]	1418	1			T12	18		T13	22		T14	28
valid_sources[0x3b]	1030	1			T11	1		T12	7		T13	19
valid_sources[0x3c]	1347	1			T11	5		T12	6		T13	21
valid_sources[0x3d]	1425	1			T11	2		T12	14		T13	24
valid_sources[0x3e]	1472	1			T11	1		T12	5		T13	23
valid_sources[0x3f]	1221	1			T12	4		T13	25		T14	17
valid_sources[0x40]	1263	1			T12	8		T13	23		T14	21
valid_sources[0x41]	1280	1			T11	17		T12	4		T13	19
valid_sources[0x42]	1410	1			T12	10		T13	20		T14	19
valid_sources[0x43]	1000	1			T6	3		T11	2		T12	5
valid_sources[0x44]	1253	1			T12	6		T13	21		T14	24
valid_sources[0x45]	1719	1			T12	14		T13	20		T14	45
valid_sources[0x46]	1377	1			T12	8		T13	30		T14	27
valid_sources[0x47]	1104	1			T8	1		T12	16		T13	26
valid_sources[0x48]	1181	1			T12	15		T13	20		T14	21
valid_sources[0x49]	1206	1			T10	27		T12	14		T13	17
valid_sources[0x4a]	1243	1			T3	22		T7	1		T10	26
valid_sources[0x4b]	1673	1			T7	1		T12	8		T13	26
valid_sources[0x4c]	1254	1			T2	1		T10	28		T12	15
valid_sources[0x4d]	996	1			T6	1		T12	13		T13	23
valid_sources[0x4e]	1390	1			T11	9		T12	26		T13	28
valid_sources[0x4f]	1491	1			T11	8		T12	16		T13	15
valid_sources[0x50]	1681	1			T12	10		T13	30		T14	25
valid_sources[0x51]	1207	1			T12	17		T13	23		T14	38
valid_sources[0x52]	1260	1			T12	12		T13	28		T14	34
valid_sources[0x53]	1589	1			T7	2		T12	12		T13	29
valid_sources[0x54]	1318	1			T12	13		T13	21		T14	28
valid_sources[0x55]	1352	1			T12	10		T13	22		T14	34
valid_sources[0x56]	1506	1			T12	8		T13	23		T14	28
valid_sources[0x57]	1503	1			T12	13		T13	20		T14	19
valid_sources[0x58]	1187	1			T8	2		T12	16		T13	23
valid_sources[0x59]	1122	1			T5	3		T7	1		T12	13
valid_sources[0x5a]	1424	1			T5	2		T6	2		T12	7
valid_sources[0x5b]	1478	1			T9	1		T11	1		T12	15
valid_sources[0x5c]	1671	1			T12	12		T13	35		T14	33
valid_sources[0x5d]	1378	1			T6	1		T11	1		T12	11
valid_sources[0x5e]	1150	1			T12	12		T13	23		T14	39
valid_sources[0x5f]	1203	1			T12	8		T13	18		T14	35
valid_sources[0x60]	1349	1			T10	3		T12	10		T13	34
valid_sources[0x61]	1119	1			T12	12		T13	23		T14	20
valid_sources[0x62]	1974	1			T12	7		T13	29		T14	35
valid_sources[0x63]	1557	1			T11	4		T12	16		T13	24
valid_sources[0x64]	1832	1			T5	1		T12	3		T13	22
valid_sources[0x65]	1217	1			T12	11		T13	23		T14	35
valid_sources[0x66]	1349	1			T9	2		T12	14		T13	26
valid_sources[0x67]	1348	1			T8	2		T12	7		T13	26
valid_sources[0x68]	1273	1			T2	1		T12	6		T13	19
valid_sources[0x69]	1285	1			T9	1		T12	8		T13	16
valid_sources[0x6a]	1266	1			T12	13		T13	25		T14	21
valid_sources[0x6b]	1411	1			T12	12		T13	20		T14	37
valid_sources[0x6c]	1069	1			T12	16		T13	35		T14	19
valid_sources[0x6d]	1187	1			T12	11		T13	29		T14	32
valid_sources[0x6e]	1049	1			T12	5		T13	21		T14	23
valid_sources[0x6f]	1749	1			T6	2		T9	2		T11	1
valid_sources[0x70]	1894	1			T11	1		T12	3		T13	16
valid_sources[0x71]	1135	1			T5	2		T12	14		T13	23
valid_sources[0x72]	1216	1			T6	1		T9	2		T11	5
valid_sources[0x73]	1222	1			T12	15		T13	40		T14	26
valid_sources[0x74]	1391	1			T12	18		T13	24		T14	26
valid_sources[0x75]	1240	1			T11	1		T12	8		T13	19
valid_sources[0x76]	1235	1			T12	12		T13	20		T14	32
valid_sources[0x77]	1478	1			T7	2		T11	6		T12	14
valid_sources[0x78]	1344	1			T11	1		T12	13		T13	20
valid_sources[0x79]	1063	1			T10	13		T12	20		T13	30
valid_sources[0x7a]	1331	1			T2	2		T10	6		T12	4
valid_sources[0x7b]	1257	1			T12	14		T13	25		T14	28
valid_sources[0x7c]	1544	1			T7	1		T12	4		T13	30
valid_sources[0x7d]	1434	1			T8	1		T10	27		T12	11
valid_sources[0x7e]	1842	1			T11	6		T12	20		T13	20
valid_sources[0x7f]	1540	1			T12	9		T13	15		T14	30
valid_sources[0x80]	1170	1			T12	12		T13	33		T14	23

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

74429

1

T1

22

T2

1

T4

1

values[0x0]

all_enables

biggest_size

113372

1

T1

96

T2

6

T3

6

values[0x1]

all_enables

biggest_size

112035

1

T1

97

T2

7

T3

9