Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	100.00	80.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	436354306	297512	0	0
wdog_bark_thold_rd_A	436354306	8770	0	0
wdog_bite_thold_rd_A	436354306	7812	0	0
wdog_ctrl_rd_A	436354306	8038	0	0
wdog_regwen_rd_A	436354306	9047	0	0
wkup_ctrl_rd_A	436354306	8152	0	0
wkup_thold_hi_rd_A	436354306	8820	0	0
wkup_thold_lo_rd_A	436354306	7815	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436354306	297512	0	0
T12	177838	3476	0	0
T13	196531	6199	0	0
T14	405195	6035	0	0
T15	54121	0	0	0
T16	200844	3408	0	0
T17	107058	0	0	0
T32	32937	0	0	0
T33	14217	0	0	0
T34	0	1463	0	0
T36	0	4685	0	0
T38	0	3063	0	0
T45	0	4492	0	0
T46	0	4519	0	0
T47	0	3995	0	0
T48	42352	0	0	0
T49	753582	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436354306	8770	0	0
T12	177838	337	0	0
T13	196531	0	0	0
T14	405195	720	0	0
T15	54121	0	0	0
T16	200844	0	0	0
T17	107058	0	0	0
T32	32937	0	0	0
T33	14217	0	0	0
T34	0	115	0	0
T36	0	307	0	0
T48	42352	0	0	0
T49	753582	0	0	0
T76	0	652	0	0
T77	0	670	0	0
T78	0	912	0	0
T79	0	1193	0	0
T80	0	85	0	0
T81	0	891	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436354306	7812	0	0
T12	177838	236	0	0
T13	196531	0	0	0
T14	405195	560	0	0
T15	54121	0	0	0
T16	200844	0	0	0
T17	107058	0	0	0
T32	32937	0	0	0
T33	14217	0	0	0
T34	0	155	0	0
T36	0	190	0	0
T48	42352	0	0	0
T49	753582	0	0	0
T76	0	594	0	0
T77	0	620	0	0
T78	0	723	0	0
T79	0	1086	0	0
T80	0	81	0	0
T81	0	715	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436354306	8038	0	0
T12	177838	264	0	0
T13	196531	0	0	0
T14	405195	584	0	0
T15	54121	0	0	0
T16	200844	0	0	0
T17	107058	0	0	0
T32	32937	0	0	0
T33	14217	0	0	0
T34	0	175	0	0
T36	0	163	0	0
T48	42352	0	0	0
T49	753582	0	0	0
T76	0	674	0	0
T77	0	556	0	0
T78	0	804	0	0
T79	0	1127	0	0
T80	0	68	0	0
T81	0	833	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436354306	9047	0	0
T12	177838	311	0	0
T13	196531	0	0	0
T14	405195	703	0	0
T15	54121	0	0	0
T16	200844	0	0	0
T17	107058	0	0	0
T32	32937	0	0	0
T33	14217	0	0	0
T34	0	157	0	0
T36	0	150	0	0
T48	42352	0	0	0
T49	753582	0	0	0
T76	0	701	0	0
T77	0	717	0	0
T78	0	945	0	0
T79	0	1288	0	0
T80	0	69	0	0
T81	0	765	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436354306	8152	0	0
T12	177838	272	0	0
T13	196531	0	0	0
T14	405195	525	0	0
T15	54121	0	0	0
T16	200844	0	0	0
T17	107058	0	0	0
T32	32937	0	0	0
T33	14217	0	0	0
T34	0	172	0	0
T36	0	206	0	0
T48	42352	0	0	0
T49	753582	0	0	0
T76	0	536	0	0
T77	0	659	0	0
T78	0	877	0	0
T79	0	1161	0	0
T80	0	102	0	0
T81	0	643	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436354306	8820	0	0
T12	177838	312	0	0
T13	196531	0	0	0
T14	405195	727	0	0
T15	54121	0	0	0
T16	200844	0	0	0
T17	107058	0	0	0
T32	32937	0	0	0
T33	14217	0	0	0
T34	0	124	0	0
T36	0	212	0	0
T48	42352	0	0	0
T49	753582	0	0	0
T76	0	759	0	0
T77	0	678	0	0
T78	0	863	0	0
T79	0	1296	0	0
T80	0	60	0	0
T81	0	940	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436354306	7815	0	0
T12	177838	326	0	0
T13	196531	0	0	0
T14	405195	685	0	0
T15	54121	0	0	0
T16	200844	0	0	0
T17	107058	0	0	0
T32	32937	0	0	0
T33	14217	0	0	0
T34	0	154	0	0
T36	0	203	0	0
T48	42352	0	0	0
T49	753582	0	0	0
T76	0	564	0	0
T77	0	457	0	0
T78	0	775	0	0
T79	0	1080	0	0
T80	0	58	0	0
T81	0	642	0	0