Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41367	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

313532

1

T1

11

T2

14

T3

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	90118	1			T1	1		T2	1		T3	1
values[0x0]	125316	1			T1	8		T2	14		T3	11
values[0x1]	139465	1			T1	11		T2	5		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25162	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

329737

1

T1

11

T2

14

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1628	1			T12	14		T15	10		T17	35
valid_sources[0x01]	1404	1			T3	3		T12	12		T13	3
valid_sources[0x02]	1286	1			T9	1		T12	19		T13	1
valid_sources[0x03]	1213	1			T12	11		T13	1		T14	1
valid_sources[0x04]	1277	1			T12	12		T14	1		T17	30
valid_sources[0x05]	1178	1			T12	19		T13	1		T17	59
valid_sources[0x06]	1191	1			T1	20		T12	15		T13	2
valid_sources[0x07]	1455	1			T12	13		T13	1		T17	62
valid_sources[0x08]	1620	1			T2	1		T12	7		T13	2
valid_sources[0x09]	1150	1			T4	3		T12	13		T14	2
valid_sources[0x0a]	1186	1			T2	1		T12	8		T14	1
valid_sources[0x0b]	1418	1			T8	1		T12	13		T13	4
valid_sources[0x0c]	1626	1			T12	11		T13	1		T14	2
valid_sources[0x0d]	1494	1			T12	5		T13	1		T34	11
valid_sources[0x0e]	1436	1			T7	2		T12	15		T14	1
valid_sources[0x0f]	1086	1			T9	2		T11	2		T12	10
valid_sources[0x10]	1316	1			T8	1		T12	11		T13	1
valid_sources[0x11]	1378	1			T12	14		T13	2		T17	59
valid_sources[0x12]	1322	1			T12	16		T13	2		T15	3
valid_sources[0x13]	1509	1			T12	19		T13	1		T14	2
valid_sources[0x14]	1383	1			T12	15		T17	40		T35	1
valid_sources[0x15]	1224	1			T3	1		T12	15		T13	1
valid_sources[0x16]	1226	1			T12	17		T14	5		T15	1
valid_sources[0x17]	1871	1			T12	9		T13	2		T14	1
valid_sources[0x18]	1214	1			T12	17		T13	1		T15	6
valid_sources[0x19]	1376	1			T2	2		T12	15		T13	1
valid_sources[0x1a]	1501	1			T12	13		T13	2		T17	47
valid_sources[0x1b]	1170	1			T2	1		T8	1		T12	10
valid_sources[0x1c]	1352	1			T12	17		T13	3		T15	3
valid_sources[0x1d]	1360	1			T12	12		T13	1		T15	7
valid_sources[0x1e]	1232	1			T12	21		T14	1		T17	20
valid_sources[0x1f]	1397	1			T12	16		T17	43		T35	2
valid_sources[0x20]	1321	1			T12	21		T13	3		T14	1
valid_sources[0x21]	1319	1			T2	1		T12	11		T14	4
valid_sources[0x22]	1577	1			T3	1		T12	12		T13	1
valid_sources[0x23]	1110	1			T12	16		T13	1		T17	36
valid_sources[0x24]	1119	1			T3	3		T12	9		T13	3
valid_sources[0x25]	1072	1			T12	14		T14	2		T15	3
valid_sources[0x26]	1801	1			T12	14		T14	1		T15	9
valid_sources[0x27]	1179	1			T12	18		T13	4		T14	1
valid_sources[0x28]	1667	1			T12	9		T13	1		T14	2
valid_sources[0x29]	1207	1			T12	8		T13	1		T15	4
valid_sources[0x2a]	1249	1			T3	1		T12	17		T13	1
valid_sources[0x2b]	1430	1			T4	3		T12	10		T13	1
valid_sources[0x2c]	1708	1			T12	8		T13	3		T14	1
valid_sources[0x2d]	1297	1			T12	14		T13	1		T14	1
valid_sources[0x2e]	1461	1			T11	1		T12	21		T13	2
valid_sources[0x2f]	1518	1			T16	22		T12	10		T13	2
valid_sources[0x30]	1201	1			T12	13		T13	2		T14	2
valid_sources[0x31]	1546	1			T12	22		T14	1		T17	23
valid_sources[0x32]	1048	1			T12	16		T13	1		T15	3
valid_sources[0x33]	1497	1			T9	3		T12	13		T13	5
valid_sources[0x34]	1171	1			T12	10		T13	1		T14	1
valid_sources[0x35]	1125	1			T12	9		T13	1		T34	13
valid_sources[0x36]	1527	1			T12	13		T13	3		T14	1
valid_sources[0x37]	1027	1			T10	22		T12	18		T13	3
valid_sources[0x38]	1569	1			T12	12		T17	29		T18	175
valid_sources[0x39]	1662	1			T12	12		T14	2		T15	1
valid_sources[0x3a]	1106	1			T12	16		T14	1		T17	33
valid_sources[0x3b]	1101	1			T8	1		T12	12		T13	1
valid_sources[0x3c]	1809	1			T8	1		T12	12		T14	1
valid_sources[0x3d]	1414	1			T12	14		T13	1		T14	1
valid_sources[0x3e]	1694	1			T12	8		T13	2		T17	44
valid_sources[0x3f]	1174	1			T12	13		T13	2		T14	1
valid_sources[0x40]	1817	1			T11	1		T12	9		T13	3
valid_sources[0x41]	1204	1			T2	1		T12	15		T14	1
valid_sources[0x42]	1744	1			T12	14		T14	1		T17	33
valid_sources[0x43]	1845	1			T12	14		T14	2		T17	31
valid_sources[0x44]	1148	1			T12	19		T14	1		T54	1
valid_sources[0x45]	1578	1			T12	14		T14	1		T54	1
valid_sources[0x46]	1197	1			T12	10		T13	3		T14	2
valid_sources[0x47]	1558	1			T12	12		T14	3		T15	4
valid_sources[0x48]	1235	1			T12	8		T13	1		T14	1
valid_sources[0x49]	1597	1			T12	9		T13	1		T15	1
valid_sources[0x4a]	1154	1			T12	13		T13	1		T14	1
valid_sources[0x4b]	1359	1			T12	18		T14	2		T15	1
valid_sources[0x4c]	1485	1			T11	4		T12	11		T17	44
valid_sources[0x4d]	1527	1			T12	6		T13	1		T15	2
valid_sources[0x4e]	1338	1			T12	13		T13	3		T14	4
valid_sources[0x4f]	1316	1			T7	1		T12	15		T13	1
valid_sources[0x50]	1215	1			T3	1		T12	10		T14	2
valid_sources[0x51]	1445	1			T12	20		T13	2		T14	4
valid_sources[0x52]	1075	1			T9	1		T12	8		T13	1
valid_sources[0x53]	1231	1			T12	20		T14	2		T34	55
valid_sources[0x54]	1627	1			T7	1		T12	13		T13	1
valid_sources[0x55]	1367	1			T12	12		T13	2		T14	1
valid_sources[0x56]	1428	1			T6	67		T12	14		T14	2
valid_sources[0x57]	1344	1			T12	14		T14	1		T17	54
valid_sources[0x58]	1462	1			T12	8		T14	1		T15	1
valid_sources[0x59]	1224	1			T12	19		T14	1		T17	64
valid_sources[0x5a]	1143	1			T8	1		T12	7		T15	2
valid_sources[0x5b]	1825	1			T5	20		T12	13		T13	1
valid_sources[0x5c]	1123	1			T12	15		T15	3		T34	3
valid_sources[0x5d]	1636	1			T12	9		T17	44		T86	1
valid_sources[0x5e]	1478	1			T12	14		T14	2		T15	3
valid_sources[0x5f]	1855	1			T2	1		T12	17		T13	1
valid_sources[0x60]	1409	1			T12	15		T13	3		T14	1
valid_sources[0x61]	1230	1			T4	1		T12	18		T15	5
valid_sources[0x62]	1270	1			T8	1		T12	9		T13	1
valid_sources[0x63]	1182	1			T12	10		T13	2		T15	3
valid_sources[0x64]	1873	1			T7	1		T12	12		T13	1
valid_sources[0x65]	1673	1			T12	13		T14	4		T17	71
valid_sources[0x66]	1023	1			T7	1		T12	15		T13	1
valid_sources[0x67]	1471	1			T12	14		T14	3		T17	43
valid_sources[0x68]	1176	1			T8	1		T12	19		T13	1
valid_sources[0x69]	1358	1			T12	8		T14	2		T17	44
valid_sources[0x6a]	1554	1			T12	11		T13	1		T17	60
valid_sources[0x6b]	1551	1			T12	12		T14	1		T15	1
valid_sources[0x6c]	1217	1			T12	7		T13	1		T14	5
valid_sources[0x6d]	1245	1			T12	19		T13	1		T14	3
valid_sources[0x6e]	2090	1			T11	2		T12	14		T13	2
valid_sources[0x6f]	1726	1			T8	1		T9	2		T12	16
valid_sources[0x70]	1144	1			T12	15		T13	1		T14	3
valid_sources[0x71]	1444	1			T12	11		T13	1		T17	36
valid_sources[0x72]	1404	1			T2	1		T9	2		T12	14
valid_sources[0x73]	1231	1			T12	18		T13	1		T14	1
valid_sources[0x74]	1723	1			T12	18		T14	2		T45	3
valid_sources[0x75]	1234	1			T7	2		T12	11		T14	1
valid_sources[0x76]	1263	1			T8	1		T12	10		T14	1
valid_sources[0x77]	1596	1			T12	15		T13	4		T45	6
valid_sources[0x78]	2017	1			T12	12		T14	1		T17	29
valid_sources[0x79]	1835	1			T12	9		T13	1		T14	1
valid_sources[0x7a]	1377	1			T12	19		T13	1		T14	1
valid_sources[0x7b]	1570	1			T12	13		T13	2		T34	4
valid_sources[0x7c]	1293	1			T12	15		T14	1		T15	1
valid_sources[0x7d]	1756	1			T12	19		T13	1		T14	1
valid_sources[0x7e]	1206	1			T7	1		T11	4		T12	10
valid_sources[0x7f]	1286	1			T12	8		T13	1		T14	2
valid_sources[0x80]	1179	1			T2	1		T6	66		T12	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

77808

1

T5

1

T6

18

T9

1

values[0x0]

all_enables

biggest_size

118063

1

T1

4

T2

10

T3

8

values[0x1]

all_enables

biggest_size

117661

1

T1

7

T2

4

T3

5