Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	100.00	80.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	619520105	315249	0	0
wdog_bark_thold_rd_A	619520105	7493	0	0
wdog_bite_thold_rd_A	619520105	6346	0	0
wdog_ctrl_rd_A	619520105	6719	0	0
wdog_regwen_rd_A	619520105	7329	0	0
wkup_ctrl_rd_A	619520105	6665	0	0
wkup_thold_hi_rd_A	619520105	6915	0	0
wkup_thold_lo_rd_A	619520105	6432	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619520105	315249	0	0
T12	111368	3507	0	0
T13	906547	0	0	0
T14	147648	0	0	0
T15	110988	0	0	0
T17	427858	10251	0	0
T18	0	1009	0	0
T33	13364	0	0	0
T34	732789	0	0	0
T45	397438	0	0	0
T46	0	554	0	0
T47	0	7109	0	0
T48	0	11190	0	0
T49	0	2431	0	0
T50	0	9573	0	0
T51	0	6275	0	0
T52	0	3505	0	0
T53	23868	0	0	0
T54	740329	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619520105	7493	0	0
T18	52413	120	0	0
T46	62217	120	0	0
T47	229348	0	0	0
T48	355479	0	0	0
T49	199438	0	0	0
T50	0	1044	0	0
T51	0	342	0	0
T80	0	152	0	0
T81	0	311	0	0
T82	0	433	0	0
T83	0	466	0	0
T84	0	944	0	0
T85	0	1180	0	0
T86	229037	0	0	0
T87	148318	0	0	0
T88	52200	0	0	0
T89	184144	0	0	0
T90	113271	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619520105	6346	0	0
T18	52413	137	0	0
T46	62217	108	0	0
T47	229348	0	0	0
T48	355479	0	0	0
T49	199438	0	0	0
T50	0	930	0	0
T51	0	365	0	0
T80	0	137	0	0
T81	0	153	0	0
T82	0	345	0	0
T83	0	453	0	0
T84	0	784	0	0
T85	0	1006	0	0
T86	229037	0	0	0
T87	148318	0	0	0
T88	52200	0	0	0
T89	184144	0	0	0
T90	113271	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619520105	6719	0	0
T18	52413	91	0	0
T46	62217	90	0	0
T47	229348	0	0	0
T48	355479	0	0	0
T49	199438	0	0	0
T50	0	916	0	0
T51	0	404	0	0
T80	0	137	0	0
T81	0	248	0	0
T82	0	360	0	0
T83	0	414	0	0
T84	0	901	0	0
T85	0	954	0	0
T86	229037	0	0	0
T87	148318	0	0	0
T88	52200	0	0	0
T89	184144	0	0	0
T90	113271	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619520105	7329	0	0
T18	52413	122	0	0
T46	62217	101	0	0
T47	229348	0	0	0
T48	355479	0	0	0
T49	199438	0	0	0
T50	0	956	0	0
T51	0	371	0	0
T80	0	142	0	0
T81	0	222	0	0
T82	0	439	0	0
T83	0	478	0	0
T84	0	862	0	0
T85	0	956	0	0
T86	229037	0	0	0
T87	148318	0	0	0
T88	52200	0	0	0
T89	184144	0	0	0
T90	113271	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619520105	6665	0	0
T18	52413	106	0	0
T46	62217	99	0	0
T47	229348	0	0	0
T48	355479	0	0	0
T49	199438	0	0	0
T50	0	862	0	0
T51	0	349	0	0
T80	0	135	0	0
T81	0	148	0	0
T82	0	348	0	0
T83	0	548	0	0
T84	0	965	0	0
T85	0	863	0	0
T86	229037	0	0	0
T87	148318	0	0	0
T88	52200	0	0	0
T89	184144	0	0	0
T90	113271	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619520105	6915	0	0
T18	52413	87	0	0
T46	62217	91	0	0
T47	229348	0	0	0
T48	355479	0	0	0
T49	199438	0	0	0
T50	0	949	0	0
T51	0	383	0	0
T80	0	171	0	0
T81	0	182	0	0
T82	0	377	0	0
T83	0	459	0	0
T84	0	937	0	0
T85	0	912	0	0
T86	229037	0	0	0
T87	148318	0	0	0
T88	52200	0	0	0
T89	184144	0	0	0
T90	113271	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619520105	6432	0	0
T18	52413	67	0	0
T46	62217	63	0	0
T47	229348	0	0	0
T48	355479	0	0	0
T49	199438	0	0	0
T50	0	896	0	0
T51	0	273	0	0
T80	0	102	0	0
T81	0	188	0	0
T82	0	448	0	0
T83	0	478	0	0
T84	0	908	0	0
T85	0	887	0	0
T86	229037	0	0	0
T87	148318	0	0	0
T88	52200	0	0	0
T89	184144	0	0	0
T90	113271	0	0	0