Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40109	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

282266

1

T1

11

T2

14

T3

246

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	82327	1			T1	1		T2	1		T3	28
values[0x0]	114078	1			T1	7		T2	10		T3	153
values[0x1]	125970	1			T1	12		T2	9		T3	157

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24807	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

297568

1

T1

12

T2

15

T3

264

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1207	1			T3	3		T6	1		T9	12
valid_sources[0x01]	1190	1			T14	12		T18	25		T27	1
valid_sources[0x02]	1018	1			T3	1		T6	2		T14	12
valid_sources[0x03]	1450	1			T14	6		T30	1		T17	2
valid_sources[0x04]	1226	1			T3	2		T6	3		T13	49
valid_sources[0x05]	1222	1			T3	1		T11	1		T14	13
valid_sources[0x06]	1350	1			T3	2		T10	1		T14	10
valid_sources[0x07]	1469	1			T3	1		T9	4		T14	14
valid_sources[0x08]	1223	1			T3	4		T14	14		T31	1
valid_sources[0x09]	1103	1			T3	1		T6	1		T14	18
valid_sources[0x0a]	979	1			T6	1		T10	1		T14	13
valid_sources[0x0b]	1298	1			T3	1		T6	3		T14	12
valid_sources[0x0c]	1284	1			T3	1		T6	3		T13	7
valid_sources[0x0d]	1619	1			T3	1		T6	1		T11	1
valid_sources[0x0e]	1339	1			T3	2		T14	17		T17	8
valid_sources[0x0f]	1077	1			T6	1		T14	12		T18	23
valid_sources[0x10]	1351	1			T6	1		T9	6		T14	12
valid_sources[0x11]	1185	1			T3	1		T6	2		T14	5
valid_sources[0x12]	1281	1			T6	1		T11	1		T14	21
valid_sources[0x13]	986	1			T6	1		T9	11		T14	15
valid_sources[0x14]	1364	1			T9	7		T14	19		T18	30
valid_sources[0x15]	1128	1			T3	2		T6	1		T14	8
valid_sources[0x16]	1139	1			T3	1		T7	1		T14	5
valid_sources[0x17]	1244	1			T3	1		T6	2		T14	12
valid_sources[0x18]	932	1			T3	1		T9	23		T14	12
valid_sources[0x19]	1140	1			T1	1		T14	10		T18	20
valid_sources[0x1a]	1415	1			T2	9		T3	1		T14	17
valid_sources[0x1b]	1215	1			T3	1		T9	1		T14	9
valid_sources[0x1c]	1414	1			T3	3		T6	1		T9	3
valid_sources[0x1d]	1383	1			T3	1		T14	20		T18	24
valid_sources[0x1e]	1163	1			T3	1		T6	1		T14	10
valid_sources[0x1f]	1049	1			T1	1		T3	4		T6	2
valid_sources[0x20]	1211	1			T6	1		T9	2		T14	7
valid_sources[0x21]	1076	1			T13	28		T14	8		T17	6
valid_sources[0x22]	1285	1			T6	3		T9	3		T14	11
valid_sources[0x23]	1268	1			T3	4		T14	7		T17	3
valid_sources[0x24]	1094	1			T3	1		T6	1		T9	3
valid_sources[0x25]	1058	1			T3	1		T6	1		T10	1
valid_sources[0x26]	985	1			T3	1		T14	15		T18	22
valid_sources[0x27]	1224	1			T3	1		T6	2		T14	7
valid_sources[0x28]	1107	1			T6	1		T8	2		T14	14
valid_sources[0x29]	1156	1			T3	3		T6	1		T14	11
valid_sources[0x2a]	1491	1			T3	2		T14	5		T17	7
valid_sources[0x2b]	1173	1			T2	1		T3	2		T10	1
valid_sources[0x2c]	1612	1			T6	3		T9	21		T14	12
valid_sources[0x2d]	1522	1			T3	1		T13	9		T14	21
valid_sources[0x2e]	1095	1			T6	1		T14	11		T16	1
valid_sources[0x2f]	1250	1			T3	1		T6	3		T7	1
valid_sources[0x30]	1154	1			T1	6		T3	1		T9	1
valid_sources[0x31]	1211	1			T3	2		T6	3		T13	21
valid_sources[0x32]	1117	1			T3	2		T6	2		T14	11
valid_sources[0x33]	830	1			T3	2		T6	1		T14	17
valid_sources[0x34]	1580	1			T3	2		T6	1		T14	19
valid_sources[0x35]	1080	1			T3	2		T11	1		T14	22
valid_sources[0x36]	1149	1			T14	16		T18	24		T27	5
valid_sources[0x37]	1268	1			T3	3		T6	2		T11	2
valid_sources[0x38]	1584	1			T6	4		T11	1		T14	17
valid_sources[0x39]	1080	1			T6	1		T14	19		T17	1
valid_sources[0x3a]	989	1			T3	1		T14	10		T18	29
valid_sources[0x3b]	1147	1			T3	2		T9	1		T10	1
valid_sources[0x3c]	1519	1			T6	2		T9	1		T14	5
valid_sources[0x3d]	1324	1			T3	2		T6	1		T14	20
valid_sources[0x3e]	1282	1			T3	2		T6	3		T14	5
valid_sources[0x3f]	975	1			T8	1		T14	12		T18	26
valid_sources[0x40]	1165	1			T3	1		T6	1		T9	3
valid_sources[0x41]	1115	1			T3	1		T7	1		T14	11
valid_sources[0x42]	1110	1			T3	1		T6	2		T14	6
valid_sources[0x43]	1216	1			T3	3		T9	9		T14	19
valid_sources[0x44]	1020	1			T3	3		T6	1		T9	4
valid_sources[0x45]	1083	1			T3	3		T6	1		T14	5
valid_sources[0x46]	1241	1			T1	2		T3	3		T6	4
valid_sources[0x47]	1474	1			T3	2		T6	1		T8	2
valid_sources[0x48]	1711	1			T3	1		T6	2		T9	9
valid_sources[0x49]	1360	1			T3	1		T14	12		T18	14
valid_sources[0x4a]	1485	1			T3	1		T6	2		T9	10
valid_sources[0x4b]	1273	1			T3	4		T6	1		T14	7
valid_sources[0x4c]	1176	1			T3	3		T6	2		T9	10
valid_sources[0x4d]	1205	1			T3	1		T9	4		T14	14
valid_sources[0x4e]	1244	1			T3	1		T6	2		T14	18
valid_sources[0x4f]	1007	1			T6	1		T7	1		T14	12
valid_sources[0x50]	1688	1			T3	3		T14	11		T17	3
valid_sources[0x51]	1567	1			T6	2		T9	1		T14	15
valid_sources[0x52]	1043	1			T3	7		T6	1		T14	11
valid_sources[0x53]	1224	1			T3	2		T6	3		T14	9
valid_sources[0x54]	1288	1			T3	1		T6	2		T14	6
valid_sources[0x55]	1119	1			T1	1		T6	6		T14	12
valid_sources[0x56]	1379	1			T6	1		T13	25		T14	16
valid_sources[0x57]	1438	1			T3	1		T6	2		T9	8
valid_sources[0x58]	1292	1			T14	19		T18	19		T27	6
valid_sources[0x59]	1056	1			T3	1		T5	1		T6	1
valid_sources[0x5a]	1414	1			T5	8		T6	2		T14	12
valid_sources[0x5b]	1036	1			T6	3		T9	1		T14	13
valid_sources[0x5c]	1102	1			T3	1		T6	2		T14	9
valid_sources[0x5d]	1242	1			T3	1		T6	1		T14	17
valid_sources[0x5e]	1403	1			T3	1		T9	9		T14	7
valid_sources[0x5f]	1109	1			T3	1		T6	3		T14	14
valid_sources[0x60]	1095	1			T6	3		T9	1		T13	22
valid_sources[0x61]	1083	1			T3	1		T14	13		T18	27
valid_sources[0x62]	1163	1			T3	1		T6	1		T14	13
valid_sources[0x63]	1105	1			T3	1		T6	1		T14	16
valid_sources[0x64]	1630	1			T3	3		T9	1		T14	10
valid_sources[0x65]	1334	1			T7	2		T14	22		T18	17
valid_sources[0x66]	1485	1			T6	1		T14	16		T17	2
valid_sources[0x67]	1175	1			T3	2		T6	1		T8	1
valid_sources[0x68]	1232	1			T3	2		T6	3		T8	1
valid_sources[0x69]	1220	1			T6	1		T14	19		T17	2
valid_sources[0x6a]	1454	1			T6	1		T12	3		T14	10
valid_sources[0x6b]	1401	1			T1	1		T3	1		T6	2
valid_sources[0x6c]	927	1			T9	2		T14	15		T18	25
valid_sources[0x6d]	1148	1			T2	1		T3	3		T14	8
valid_sources[0x6e]	1260	1			T3	2		T6	1		T14	21
valid_sources[0x6f]	1179	1			T11	1		T14	15		T17	3
valid_sources[0x70]	1316	1			T3	1		T10	1		T14	26
valid_sources[0x71]	1225	1			T3	3		T6	1		T9	1
valid_sources[0x72]	1547	1			T3	2		T14	18		T18	21
valid_sources[0x73]	1175	1			T6	1		T11	1		T14	21
valid_sources[0x74]	1450	1			T3	1		T6	3		T14	11
valid_sources[0x75]	1425	1			T6	3		T9	4		T14	16
valid_sources[0x76]	1076	1			T6	4		T14	10		T18	21
valid_sources[0x77]	1243	1			T5	1		T14	13		T30	1
valid_sources[0x78]	1164	1			T3	1		T6	3		T14	10
valid_sources[0x79]	1157	1			T3	1		T6	2		T14	8
valid_sources[0x7a]	1557	1			T6	1		T10	1		T14	23
valid_sources[0x7b]	1466	1			T3	2		T6	2		T7	1
valid_sources[0x7c]	1022	1			T6	2		T14	10		T25	1
valid_sources[0x7d]	1183	1			T3	2		T5	1		T6	2
valid_sources[0x7e]	1447	1			T6	2		T10	2		T14	4
valid_sources[0x7f]	981	1			T6	4		T14	9		T18	29
valid_sources[0x80]	1360	1			T2	1		T3	3		T6	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

69859

1

T3

14

T4

1

T6

22

values[0x0]

all_enables

biggest_size

106963

1

T1

3

T2

9

T3

115

values[0x1]

all_enables

biggest_size

105444

1

T1

8

T2

5

T3

117