Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	100.00	80.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	581274831	286224	0	0
wdog_bark_thold_rd_A	581274831	7292	0	0
wdog_bite_thold_rd_A	581274831	6402	0	0
wdog_ctrl_rd_A	581274831	6794	0	0
wdog_regwen_rd_A	581274831	7203	0	0
wkup_ctrl_rd_A	581274831	6791	0	0
wkup_thold_hi_rd_A	581274831	7144	0	0
wkup_thold_lo_rd_A	581274831	6588	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581274831	286224	0	0
T14	266829	3773	0	0
T15	49452	0	0	0
T16	10711	0	0	0
T17	902519	0	0	0
T18	214619	5427	0	0
T19	0	3244	0	0
T20	758044	0	0	0
T25	47452	0	0	0
T26	24507	0	0	0
T28	0	2348	0	0
T30	20701	0	0	0
T31	9394	0	0	0
T38	0	4331	0	0
T39	0	5246	0	0
T40	0	11928	0	0
T41	0	3542	0	0
T42	0	2799	0	0
T43	0	5195	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581274831	7292	0	0
T39	294457	310	0	0
T41	0	329	0	0
T76	0	205	0	0
T77	0	568	0	0
T78	0	617	0	0
T79	0	439	0	0
T80	0	381	0	0
T81	0	397	0	0
T82	0	182	0	0
T83	0	978	0	0
T84	169341	0	0	0
T85	27255	0	0	0
T86	13506	0	0	0
T87	407579	0	0	0
T88	34521	0	0	0
T89	749840	0	0	0
T90	254723	0	0	0
T91	45098	0	0	0
T92	143279	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581274831	6402	0	0
T39	294457	277	0	0
T41	0	279	0	0
T76	0	152	0	0
T77	0	398	0	0
T78	0	483	0	0
T79	0	469	0	0
T80	0	371	0	0
T81	0	364	0	0
T82	0	183	0	0
T83	0	863	0	0
T84	169341	0	0	0
T85	27255	0	0	0
T86	13506	0	0	0
T87	407579	0	0	0
T88	34521	0	0	0
T89	749840	0	0	0
T90	254723	0	0	0
T91	45098	0	0	0
T92	143279	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581274831	6794	0	0
T39	294457	250	0	0
T41	0	338	0	0
T76	0	228	0	0
T77	0	507	0	0
T78	0	429	0	0
T79	0	449	0	0
T80	0	328	0	0
T81	0	422	0	0
T82	0	160	0	0
T83	0	845	0	0
T84	169341	0	0	0
T85	27255	0	0	0
T86	13506	0	0	0
T87	407579	0	0	0
T88	34521	0	0	0
T89	749840	0	0	0
T90	254723	0	0	0
T91	45098	0	0	0
T92	143279	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581274831	7203	0	0
T39	294457	299	0	0
T41	0	374	0	0
T76	0	160	0	0
T77	0	609	0	0
T78	0	476	0	0
T79	0	434	0	0
T80	0	483	0	0
T81	0	449	0	0
T82	0	176	0	0
T83	0	903	0	0
T84	169341	0	0	0
T85	27255	0	0	0
T86	13506	0	0	0
T87	407579	0	0	0
T88	34521	0	0	0
T89	749840	0	0	0
T90	254723	0	0	0
T91	45098	0	0	0
T92	143279	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581274831	6791	0	0
T39	294457	222	0	0
T41	0	234	0	0
T76	0	189	0	0
T77	0	595	0	0
T78	0	599	0	0
T79	0	431	0	0
T80	0	309	0	0
T81	0	292	0	0
T82	0	182	0	0
T83	0	864	0	0
T84	169341	0	0	0
T85	27255	0	0	0
T86	13506	0	0	0
T87	407579	0	0	0
T88	34521	0	0	0
T89	749840	0	0	0
T90	254723	0	0	0
T91	45098	0	0	0
T92	143279	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581274831	7144	0	0
T39	294457	303	0	0
T41	0	376	0	0
T76	0	179	0	0
T77	0	556	0	0
T78	0	491	0	0
T79	0	578	0	0
T80	0	387	0	0
T81	0	407	0	0
T82	0	196	0	0
T83	0	891	0	0
T84	169341	0	0	0
T85	27255	0	0	0
T86	13506	0	0	0
T87	407579	0	0	0
T88	34521	0	0	0
T89	749840	0	0	0
T90	254723	0	0	0
T91	45098	0	0	0
T92	143279	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	581274831	6588	0	0
T39	294457	255	0	0
T41	0	346	0	0
T76	0	190	0	0
T77	0	546	0	0
T78	0	534	0	0
T79	0	395	0	0
T80	0	301	0	0
T81	0	362	0	0
T82	0	143	0	0
T83	0	875	0	0
T84	169341	0	0	0
T85	27255	0	0	0
T86	13506	0	0	0
T87	407579	0	0	0
T88	34521	0	0	0
T89	749840	0	0	0
T90	254723	0	0	0
T91	45098	0	0	0
T92	143279	0	0	0