Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43159	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

325846

1

T1

13

T2

15

T3

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	92764	1			T1	1		T2	1		T3	1
values[0x0]	131099	1			T1	7		T2	11		T3	12
values[0x1]	145142	1			T1	10		T2	10		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25835	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

343170

1

T1

14

T2

17

T3

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1278	1			T12	16		T16	2		T18	32
valid_sources[0x01]	1842	1			T12	15		T16	9		T44	3
valid_sources[0x02]	1672	1			T12	20		T25	1		T18	40
valid_sources[0x03]	1599	1			T12	10		T16	2		T18	33
valid_sources[0x04]	1465	1			T7	1		T12	17		T18	29
valid_sources[0x05]	1720	1			T1	1		T9	1		T12	7
valid_sources[0x06]	1378	1			T12	20		T18	33		T38	41
valid_sources[0x07]	1284	1			T10	2		T12	15		T13	17
valid_sources[0x08]	1271	1			T8	1		T12	19		T16	1
valid_sources[0x09]	1483	1			T12	11		T16	4		T18	27
valid_sources[0x0a]	962	1			T12	26		T45	1		T18	25
valid_sources[0x0b]	1204	1			T7	1		T8	1		T12	11
valid_sources[0x0c]	1473	1			T7	1		T12	8		T16	1
valid_sources[0x0d]	1389	1			T12	18		T16	1		T18	17
valid_sources[0x0e]	1093	1			T6	1		T12	16		T16	53
valid_sources[0x0f]	1655	1			T12	27		T14	1		T16	1
valid_sources[0x10]	1285	1			T12	8		T15	1		T25	3
valid_sources[0x11]	1343	1			T12	5		T16	2		T18	34
valid_sources[0x12]	1395	1			T1	1		T12	8		T18	35
valid_sources[0x13]	1477	1			T1	1		T12	17		T16	3
valid_sources[0x14]	1621	1			T1	2		T12	12		T16	5
valid_sources[0x15]	1835	1			T12	4		T24	4		T16	6
valid_sources[0x16]	1399	1			T12	13		T16	1		T18	28
valid_sources[0x17]	1066	1			T12	16		T14	1		T16	1
valid_sources[0x18]	1509	1			T10	1		T12	6		T18	31
valid_sources[0x19]	1111	1			T10	2		T12	19		T18	31
valid_sources[0x1a]	1424	1			T12	15		T18	25		T48	11
valid_sources[0x1b]	1521	1			T7	1		T12	19		T16	11
valid_sources[0x1c]	1292	1			T6	1		T12	13		T13	2
valid_sources[0x1d]	1383	1			T9	1		T10	1		T12	9
valid_sources[0x1e]	1309	1			T12	16		T16	1		T25	1
valid_sources[0x1f]	1099	1			T12	6		T45	1		T18	25
valid_sources[0x20]	1743	1			T12	8		T16	2		T18	26
valid_sources[0x21]	1586	1			T12	3		T18	28		T38	34
valid_sources[0x22]	1144	1			T7	2		T9	1		T12	24
valid_sources[0x23]	1675	1			T12	13		T16	87		T18	25
valid_sources[0x24]	1208	1			T12	8		T16	21		T18	29
valid_sources[0x25]	1275	1			T2	4		T7	1		T12	12
valid_sources[0x26]	2042	1			T12	9		T18	25		T38	43
valid_sources[0x27]	1103	1			T12	18		T45	1		T18	34
valid_sources[0x28]	1400	1			T12	6		T208	1		T18	22
valid_sources[0x29]	1405	1			T9	1		T12	13		T211	1
valid_sources[0x2a]	1098	1			T8	1		T12	4		T14	1
valid_sources[0x2b]	1106	1			T10	1		T12	7		T24	2
valid_sources[0x2c]	1309	1			T12	15		T13	8		T16	62
valid_sources[0x2d]	1494	1			T12	9		T45	1		T18	26
valid_sources[0x2e]	1463	1			T12	13		T16	34		T18	34
valid_sources[0x2f]	1296	1			T12	17		T18	29		T27	1
valid_sources[0x30]	1285	1			T12	20		T16	9		T211	1
valid_sources[0x31]	1332	1			T3	2		T6	1		T12	8
valid_sources[0x32]	1731	1			T12	12		T18	24		T38	33
valid_sources[0x33]	1103	1			T12	12		T18	25		T38	34
valid_sources[0x34]	2001	1			T12	18		T16	1		T18	32
valid_sources[0x35]	1106	1			T12	8		T13	9		T16	15
valid_sources[0x36]	1703	1			T9	1		T12	9		T16	228
valid_sources[0x37]	1142	1			T2	7		T12	1		T211	1
valid_sources[0x38]	1621	1			T9	1		T12	14		T16	1
valid_sources[0x39]	1347	1			T8	1		T9	2		T12	10
valid_sources[0x3a]	1324	1			T12	11		T16	1		T18	37
valid_sources[0x3b]	1405	1			T6	1		T12	8		T208	1
valid_sources[0x3c]	1641	1			T12	10		T13	4		T14	1
valid_sources[0x3d]	1690	1			T12	14		T18	35		T38	42
valid_sources[0x3e]	1434	1			T8	1		T12	15		T18	24
valid_sources[0x3f]	1234	1			T12	19		T16	1		T208	1
valid_sources[0x40]	1558	1			T5	19		T9	1		T12	19
valid_sources[0x41]	1261	1			T3	1		T9	1		T12	19
valid_sources[0x42]	1000	1			T12	13		T13	2		T18	27
valid_sources[0x43]	988	1			T6	1		T12	19		T208	1
valid_sources[0x44]	1311	1			T12	15		T18	26		T38	25
valid_sources[0x45]	1606	1			T12	22		T14	1		T18	26
valid_sources[0x46]	1227	1			T12	17		T26	4		T18	29
valid_sources[0x47]	1556	1			T7	2		T12	5		T44	1
valid_sources[0x48]	1489	1			T12	13		T16	13		T18	19
valid_sources[0x49]	1454	1			T6	1		T8	1		T12	8
valid_sources[0x4a]	1272	1			T6	1		T12	17		T16	2
valid_sources[0x4b]	1097	1			T12	14		T16	6		T18	27
valid_sources[0x4c]	1198	1			T9	1		T12	2		T14	1
valid_sources[0x4d]	1342	1			T12	16		T16	177		T18	41
valid_sources[0x4e]	1140	1			T12	11		T16	183		T18	29
valid_sources[0x4f]	1576	1			T6	1		T12	17		T18	31
valid_sources[0x50]	1405	1			T12	7		T16	1		T25	1
valid_sources[0x51]	1522	1			T12	15		T16	2		T45	1
valid_sources[0x52]	1287	1			T12	18		T16	5		T18	21
valid_sources[0x53]	1188	1			T9	1		T12	10		T18	24
valid_sources[0x54]	1419	1			T12	13		T18	40		T38	39
valid_sources[0x55]	1809	1			T9	1		T12	11		T16	2
valid_sources[0x56]	1640	1			T12	23		T18	15		T38	42
valid_sources[0x57]	1360	1			T12	9		T16	1		T18	39
valid_sources[0x58]	1622	1			T8	1		T12	22		T16	68
valid_sources[0x59]	1535	1			T1	1		T12	5		T18	28
valid_sources[0x5a]	1399	1			T12	16		T16	3		T18	26
valid_sources[0x5b]	1895	1			T12	13		T16	133		T45	1
valid_sources[0x5c]	1300	1			T8	1		T12	22		T16	101
valid_sources[0x5d]	1071	1			T12	27		T26	18		T18	30
valid_sources[0x5e]	1186	1			T12	9		T16	2		T18	27
valid_sources[0x5f]	1256	1			T12	15		T13	19		T18	28
valid_sources[0x60]	1807	1			T12	10		T14	1		T18	20
valid_sources[0x61]	1352	1			T6	1		T9	1		T12	20
valid_sources[0x62]	1583	1			T1	1		T12	8		T16	26
valid_sources[0x63]	1050	1			T8	1		T12	6		T18	31
valid_sources[0x64]	1465	1			T8	1		T12	14		T18	19
valid_sources[0x65]	1326	1			T12	13		T18	27		T38	25
valid_sources[0x66]	1347	1			T12	22		T16	1		T18	28
valid_sources[0x67]	1233	1			T12	16		T45	1		T18	33
valid_sources[0x68]	1926	1			T12	13		T45	1		T208	1
valid_sources[0x69]	2054	1			T12	9		T14	2		T16	5
valid_sources[0x6a]	1848	1			T12	9		T24	6		T16	168
valid_sources[0x6b]	1064	1			T12	14		T18	34		T38	30
valid_sources[0x6c]	1373	1			T10	3		T12	15		T16	4
valid_sources[0x6d]	1007	1			T12	13		T16	5		T18	19
valid_sources[0x6e]	1384	1			T7	1		T12	10		T18	29
valid_sources[0x6f]	1392	1			T1	1		T6	1		T12	15
valid_sources[0x70]	1347	1			T12	11		T13	25		T15	1
valid_sources[0x71]	1552	1			T12	14		T16	70		T18	24
valid_sources[0x72]	1750	1			T7	1		T12	8		T18	34
valid_sources[0x73]	1437	1			T12	6		T16	1		T211	1
valid_sources[0x74]	1198	1			T12	12		T16	1		T18	31
valid_sources[0x75]	1308	1			T6	1		T12	22		T16	95
valid_sources[0x76]	2204	1			T12	21		T16	181		T44	1
valid_sources[0x77]	2036	1			T6	1		T12	15		T18	21
valid_sources[0x78]	1581	1			T12	6		T13	1		T14	1
valid_sources[0x79]	1255	1			T12	6		T16	61		T211	1
valid_sources[0x7a]	1619	1			T12	6		T18	31		T38	27
valid_sources[0x7b]	1551	1			T3	6		T12	10		T16	6
valid_sources[0x7c]	1745	1			T12	33		T211	1		T18	33
valid_sources[0x7d]	1440	1			T12	11		T16	51		T18	35
valid_sources[0x7e]	1156	1			T12	17		T18	37		T38	42
valid_sources[0x7f]	1534	1			T12	10		T16	4		T44	1
valid_sources[0x80]	1465	1			T12	10		T18	30		T38	42

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

80233

1

T2

1

T3

1

T4

1

values[0x0]

all_enables

biggest_size

123579

1

T1

5

T2

9

T3

9

values[0x1]

all_enables

biggest_size

122034

1

T1

8

T2

5

T3

4