Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	100.00	80.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	432583434	336989	0	0
wdog_bark_thold_rd_A	432583434	5978	0	0
wdog_bite_thold_rd_A	432583434	5529	0	0
wdog_ctrl_rd_A	432583434	5425	0	0
wdog_regwen_rd_A	432583434	5788	0	0
wkup_ctrl_rd_A	432583434	5734	0	0
wkup_thold_hi_rd_A	432583434	5877	0	0
wkup_thold_lo_rd_A	432583434	5468	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432583434	336989	0	0
T12	153763	2765	0	0
T13	159790	0	0	0
T14	10324	0	0	0
T15	19279	0	0	0
T16	206097	5522	0	0
T18	0	7835	0	0
T19	368739	0	0	0
T24	57156	0	0	0
T26	10581	0	0	0
T28	0	6526	0	0
T38	0	10558	0	0
T39	0	2882	0	0
T40	0	9204	0	0
T41	0	4871	0	0
T42	0	8339	0	0
T43	0	1842	0	0
T44	117715	0	0	0
T45	15632	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432583434	5978	0	0
T12	153763	320	0	0
T13	159790	0	0	0
T14	10324	0	0	0
T15	19279	0	0	0
T16	206097	0	0	0
T19	368739	0	0	0
T24	57156	0	0	0
T26	10581	0	0	0
T28	0	747	0	0
T39	0	356	0	0
T41	0	343	0	0
T44	117715	0	0	0
T45	15632	0	0	0
T79	0	358	0	0
T80	0	87	0	0
T81	0	515	0	0
T82	0	501	0	0
T83	0	480	0	0
T84	0	621	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432583434	5529	0	0
T12	153763	217	0	0
T13	159790	0	0	0
T14	10324	0	0	0
T15	19279	0	0	0
T16	206097	0	0	0
T19	368739	0	0	0
T24	57156	0	0	0
T26	10581	0	0	0
T28	0	608	0	0
T39	0	354	0	0
T41	0	443	0	0
T44	117715	0	0	0
T45	15632	0	0	0
T79	0	320	0	0
T80	0	86	0	0
T81	0	443	0	0
T82	0	423	0	0
T83	0	373	0	0
T84	0	634	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432583434	5425	0	0
T12	153763	273	0	0
T13	159790	0	0	0
T14	10324	0	0	0
T15	19279	0	0	0
T16	206097	0	0	0
T19	368739	0	0	0
T24	57156	0	0	0
T26	10581	0	0	0
T28	0	696	0	0
T39	0	298	0	0
T41	0	380	0	0
T44	117715	0	0	0
T45	15632	0	0	0
T79	0	284	0	0
T80	0	82	0	0
T81	0	361	0	0
T82	0	487	0	0
T83	0	298	0	0
T84	0	511	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432583434	5788	0	0
T12	153763	307	0	0
T13	159790	0	0	0
T14	10324	0	0	0
T15	19279	0	0	0
T16	206097	0	0	0
T19	368739	0	0	0
T24	57156	0	0	0
T26	10581	0	0	0
T28	0	806	0	0
T39	0	242	0	0
T41	0	353	0	0
T44	117715	0	0	0
T45	15632	0	0	0
T79	0	394	0	0
T80	0	84	0	0
T81	0	425	0	0
T82	0	523	0	0
T83	0	354	0	0
T84	0	566	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432583434	5734	0	0
T12	153763	295	0	0
T13	159790	0	0	0
T14	10324	0	0	0
T15	19279	0	0	0
T16	206097	0	0	0
T19	368739	0	0	0
T24	57156	0	0	0
T26	10581	0	0	0
T28	0	614	0	0
T39	0	213	0	0
T41	0	372	0	0
T44	117715	0	0	0
T45	15632	0	0	0
T79	0	320	0	0
T80	0	139	0	0
T81	0	375	0	0
T82	0	402	0	0
T83	0	383	0	0
T84	0	694	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432583434	5877	0	0
T12	153763	272	0	0
T13	159790	0	0	0
T14	10324	0	0	0
T15	19279	0	0	0
T16	206097	0	0	0
T19	368739	0	0	0
T24	57156	0	0	0
T26	10581	0	0	0
T28	0	762	0	0
T39	0	256	0	0
T41	0	469	0	0
T44	117715	0	0	0
T45	15632	0	0	0
T79	0	337	0	0
T80	0	73	0	0
T81	0	533	0	0
T82	0	452	0	0
T83	0	463	0	0
T84	0	656	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432583434	5468	0	0
T12	153763	302	0	0
T13	159790	0	0	0
T14	10324	0	0	0
T15	19279	0	0	0
T16	206097	0	0	0
T19	368739	0	0	0
T24	57156	0	0	0
T26	10581	0	0	0
T28	0	707	0	0
T39	0	240	0	0
T41	0	352	0	0
T44	117715	0	0	0
T45	15632	0	0	0
T79	0	338	0	0
T80	0	98	0	0
T81	0	383	0	0
T82	0	459	0	0
T83	0	317	0	0
T84	0	631	0	0