Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40633	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

302085

1

T1

12

T2

18

T3

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	86776	1			T1	1		T2	1		T3	1
values[0x0]	121707	1			T1	10		T2	14		T3	12
values[0x1]	134235	1			T1	8		T2	7		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24963	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

317755

1

T1

14

T2

18

T3

17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1431	1			T1	1		T13	6		T16	14
valid_sources[0x01]	1688	1			T9	1		T13	6		T16	30
valid_sources[0x02]	1248	1			T13	9		T16	15		T17	11
valid_sources[0x03]	1027	1			T2	2		T6	2		T13	6
valid_sources[0x04]	1021	1			T13	10		T15	2		T16	91
valid_sources[0x05]	1126	1			T13	4		T16	30		T17	15
valid_sources[0x06]	1075	1			T13	6		T16	26		T17	6
valid_sources[0x07]	1062	1			T1	1		T13	7		T15	16
valid_sources[0x08]	1314	1			T13	7		T16	39		T17	11
valid_sources[0x09]	1357	1			T13	9		T16	21		T17	13
valid_sources[0x0a]	1427	1			T6	1		T9	1		T13	5
valid_sources[0x0b]	1264	1			T13	8		T16	14		T17	12
valid_sources[0x0c]	1588	1			T9	1		T13	1		T16	38
valid_sources[0x0d]	1137	1			T13	9		T14	1		T16	2
valid_sources[0x0e]	1354	1			T9	1		T13	5		T25	1
valid_sources[0x0f]	1356	1			T13	7		T16	17		T17	13
valid_sources[0x10]	1909	1			T10	1		T13	5		T16	5
valid_sources[0x11]	1760	1			T13	7		T16	9		T17	21
valid_sources[0x12]	1416	1			T13	4		T15	1		T16	5
valid_sources[0x13]	1116	1			T13	6		T16	14		T17	9
valid_sources[0x14]	1154	1			T9	1		T13	7		T16	13
valid_sources[0x15]	943	1			T10	1		T13	3		T15	2
valid_sources[0x16]	1068	1			T13	13		T16	11		T17	15
valid_sources[0x17]	1307	1			T13	6		T15	10		T16	27
valid_sources[0x18]	1383	1			T13	9		T16	4		T17	17
valid_sources[0x19]	1352	1			T13	7		T16	3		T17	10
valid_sources[0x1a]	874	1			T13	7		T16	2		T17	11
valid_sources[0x1b]	1114	1			T6	2		T10	1		T13	6
valid_sources[0x1c]	1662	1			T6	2		T13	3		T16	8
valid_sources[0x1d]	1174	1			T1	1		T13	7		T15	2
valid_sources[0x1e]	1318	1			T13	3		T16	14		T17	17
valid_sources[0x1f]	1179	1			T13	10		T15	4		T16	12
valid_sources[0x20]	1039	1			T13	5		T16	10		T17	12
valid_sources[0x21]	1010	1			T13	6		T16	19		T17	14
valid_sources[0x22]	1327	1			T1	1		T13	5		T17	13
valid_sources[0x23]	1352	1			T1	1		T13	3		T16	30
valid_sources[0x24]	982	1			T13	4		T15	1		T16	10
valid_sources[0x25]	1235	1			T13	3		T25	2		T15	3
valid_sources[0x26]	1854	1			T13	11		T15	5		T16	11
valid_sources[0x27]	1049	1			T13	11		T15	2		T16	8
valid_sources[0x28]	1632	1			T2	1		T13	5		T16	42
valid_sources[0x29]	1487	1			T13	8		T16	3		T17	5
valid_sources[0x2a]	1344	1			T1	1		T6	2		T9	1
valid_sources[0x2b]	1195	1			T13	9		T16	4		T17	9
valid_sources[0x2c]	1419	1			T9	2		T13	12		T15	6
valid_sources[0x2d]	1148	1			T13	11		T16	4		T17	13
valid_sources[0x2e]	1398	1			T13	5		T15	9		T16	17
valid_sources[0x2f]	1194	1			T13	10		T15	2		T16	3
valid_sources[0x30]	1191	1			T13	4		T15	4		T16	6
valid_sources[0x31]	901	1			T13	5		T14	1		T15	6
valid_sources[0x32]	1118	1			T13	12		T16	7		T17	10
valid_sources[0x33]	1488	1			T13	7		T16	30		T17	8
valid_sources[0x34]	963	1			T13	8		T16	16		T17	12
valid_sources[0x35]	1656	1			T13	9		T16	7		T17	15
valid_sources[0x36]	1164	1			T13	9		T16	34		T17	8
valid_sources[0x37]	1700	1			T13	5		T16	3		T17	9
valid_sources[0x38]	1377	1			T2	1		T13	9		T16	4
valid_sources[0x39]	1370	1			T13	9		T16	14		T17	12
valid_sources[0x3a]	1040	1			T1	1		T13	4		T16	1
valid_sources[0x3b]	1333	1			T8	20		T13	3		T15	26
valid_sources[0x3c]	1212	1			T13	7		T15	3		T16	37
valid_sources[0x3d]	1601	1			T13	7		T14	1		T16	23
valid_sources[0x3e]	1127	1			T1	1		T13	8		T16	2
valid_sources[0x3f]	1381	1			T5	1		T13	5		T16	25
valid_sources[0x40]	1553	1			T13	5		T16	3		T17	17
valid_sources[0x41]	1580	1			T13	9		T16	20		T17	12
valid_sources[0x42]	1123	1			T13	11		T15	9		T16	1
valid_sources[0x43]	1073	1			T10	1		T13	8		T16	13
valid_sources[0x44]	1522	1			T13	5		T16	33		T17	9
valid_sources[0x45]	1100	1			T13	8		T16	9		T17	18
valid_sources[0x46]	1244	1			T13	3		T16	33		T17	14
valid_sources[0x47]	1116	1			T13	5		T16	34		T17	16
valid_sources[0x48]	1095	1			T13	6		T16	22		T17	18
valid_sources[0x49]	1258	1			T2	1		T13	8		T16	11
valid_sources[0x4a]	1741	1			T13	4		T15	7		T16	5
valid_sources[0x4b]	1158	1			T13	10		T16	14		T17	9
valid_sources[0x4c]	1587	1			T13	6		T16	11		T17	21
valid_sources[0x4d]	1330	1			T1	1		T13	4		T16	7
valid_sources[0x4e]	989	1			T13	3		T17	15		T19	13
valid_sources[0x4f]	1166	1			T9	1		T13	4		T15	1
valid_sources[0x50]	1303	1			T1	1		T3	1		T10	1
valid_sources[0x51]	1231	1			T13	9		T16	14		T17	11
valid_sources[0x52]	1606	1			T13	2		T16	13		T17	18
valid_sources[0x53]	1278	1			T13	7		T16	1		T17	11
valid_sources[0x54]	1685	1			T13	9		T16	11		T17	12
valid_sources[0x55]	1308	1			T5	1		T13	5		T16	5
valid_sources[0x56]	1244	1			T5	1		T13	6		T16	16
valid_sources[0x57]	1158	1			T9	1		T13	4		T16	35
valid_sources[0x58]	1604	1			T13	7		T16	36		T17	10
valid_sources[0x59]	1311	1			T13	8		T14	3		T16	31
valid_sources[0x5a]	1840	1			T3	7		T13	4		T15	1
valid_sources[0x5b]	1402	1			T13	7		T16	21		T17	7
valid_sources[0x5c]	1138	1			T6	1		T14	1		T16	33
valid_sources[0x5d]	1278	1			T13	5		T15	2		T16	12
valid_sources[0x5e]	1733	1			T13	6		T15	11		T16	46
valid_sources[0x5f]	1044	1			T9	1		T13	5		T16	31
valid_sources[0x60]	1092	1			T13	5		T16	8		T17	6
valid_sources[0x61]	1246	1			T13	4		T16	6		T17	12
valid_sources[0x62]	1648	1			T7	22		T13	5		T25	1
valid_sources[0x63]	1177	1			T13	8		T16	26		T17	11
valid_sources[0x64]	1072	1			T13	4		T15	2		T16	14
valid_sources[0x65]	1498	1			T13	3		T16	18		T17	10
valid_sources[0x66]	1185	1			T2	1		T13	8		T48	18
valid_sources[0x67]	1503	1			T13	1		T15	8		T16	8
valid_sources[0x68]	1546	1			T13	5		T16	9		T17	14
valid_sources[0x69]	1171	1			T2	2		T13	2		T16	23
valid_sources[0x6a]	1442	1			T2	1		T5	1		T13	4
valid_sources[0x6b]	1224	1			T10	1		T13	6		T16	6
valid_sources[0x6c]	1626	1			T13	1		T16	37		T17	14
valid_sources[0x6d]	1165	1			T13	8		T25	1		T16	1
valid_sources[0x6e]	1374	1			T13	4		T25	2		T14	1
valid_sources[0x6f]	1312	1			T13	8		T14	1		T16	30
valid_sources[0x70]	1672	1			T1	1		T13	5		T14	1
valid_sources[0x71]	1284	1			T13	4		T16	37		T17	16
valid_sources[0x72]	1117	1			T13	6		T15	1		T16	3
valid_sources[0x73]	1204	1			T13	11		T16	14		T17	14
valid_sources[0x74]	1255	1			T13	7		T16	1		T17	14
valid_sources[0x75]	1101	1			T6	3		T13	5		T15	2
valid_sources[0x76]	1535	1			T2	1		T13	7		T25	2
valid_sources[0x77]	1518	1			T5	1		T13	11		T16	12
valid_sources[0x78]	1709	1			T13	3		T16	26		T17	15
valid_sources[0x79]	1671	1			T13	10		T16	27		T17	16
valid_sources[0x7a]	1253	1			T13	8		T16	4		T17	16
valid_sources[0x7b]	950	1			T13	7		T16	32		T17	11
valid_sources[0x7c]	1257	1			T9	1		T13	9		T15	5
valid_sources[0x7d]	1210	1			T13	3		T16	10		T17	13
valid_sources[0x7e]	1126	1			T4	18		T13	2		T16	5
valid_sources[0x7f]	1305	1			T10	1		T13	10		T16	16
valid_sources[0x80]	1224	1			T13	6		T16	17		T17	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

74528

1

T2

1

T3

1

T4

1

values[0x0]

all_enables

biggest_size

114588

1

T1

8

T2

10

T3

10

values[0x1]

all_enables

biggest_size

112969

1

T1

4

T2

7

T3

6