Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	100.00	80.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	468637740	304080	0	0
wdog_bark_thold_rd_A	468637740	4821	0	0
wdog_bite_thold_rd_A	468637740	4059	0	0
wdog_ctrl_rd_A	468637740	4510	0	0
wdog_regwen_rd_A	468637740	4827	0	0
wkup_ctrl_rd_A	468637740	4470	0	0
wkup_thold_hi_rd_A	468637740	5058	0	0
wkup_thold_lo_rd_A	468637740	4335	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468637740	304080	0	0
T13	80414	1626	0	0
T14	52220	0	0	0
T15	998908	0	0	0
T16	259211	5419	0	0
T17	0	1884	0	0
T18	0	7778	0	0
T19	0	2003	0	0
T23	46954	0	0	0
T24	52621	0	0	0
T25	18332	0	0	0
T27	37980	0	0	0
T31	0	3686	0	0
T37	0	16694	0	0
T44	0	6801	0	0
T45	0	11006	0	0
T46	0	10504	0	0
T47	53421	0	0	0
T48	48213	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468637740	4821	0	0
T18	412878	476	0	0
T19	184637	0	0	0
T28	14644	0	0	0
T29	5042	0	0	0
T31	0	349	0	0
T35	112139	0	0	0
T45	0	535	0	0
T49	318149	0	0	0
T50	47863	0	0	0
T51	39767	0	0	0
T80	0	208	0	0
T81	0	433	0	0
T82	0	242	0	0
T83	0	264	0	0
T84	0	326	0	0
T85	0	231	0	0
T86	0	220	0	0
T87	657652	0	0	0
T88	27649	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468637740	4059	0	0
T18	412878	411	0	0
T19	184637	0	0	0
T28	14644	0	0	0
T29	5042	0	0	0
T31	0	296	0	0
T35	112139	0	0	0
T45	0	520	0	0
T49	318149	0	0	0
T50	47863	0	0	0
T51	39767	0	0	0
T80	0	237	0	0
T81	0	355	0	0
T82	0	151	0	0
T83	0	181	0	0
T84	0	328	0	0
T85	0	196	0	0
T86	0	165	0	0
T87	657652	0	0	0
T88	27649	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468637740	4510	0	0
T18	412878	456	0	0
T19	184637	0	0	0
T28	14644	0	0	0
T29	5042	0	0	0
T31	0	291	0	0
T35	112139	0	0	0
T45	0	527	0	0
T49	318149	0	0	0
T50	47863	0	0	0
T51	39767	0	0	0
T80	0	294	0	0
T81	0	448	0	0
T82	0	150	0	0
T83	0	299	0	0
T84	0	265	0	0
T85	0	175	0	0
T86	0	153	0	0
T87	657652	0	0	0
T88	27649	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468637740	4827	0	0
T18	412878	496	0	0
T19	184637	0	0	0
T28	14644	0	0	0
T29	5042	0	0	0
T31	0	290	0	0
T35	112139	0	0	0
T45	0	645	0	0
T49	318149	0	0	0
T50	47863	0	0	0
T51	39767	0	0	0
T80	0	352	0	0
T81	0	504	0	0
T82	0	196	0	0
T83	0	242	0	0
T84	0	308	0	0
T85	0	285	0	0
T86	0	173	0	0
T87	657652	0	0	0
T88	27649	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468637740	4470	0	0
T18	412878	439	0	0
T19	184637	0	0	0
T28	14644	0	0	0
T29	5042	0	0	0
T31	0	308	0	0
T35	112139	0	0	0
T45	0	414	0	0
T49	318149	0	0	0
T50	47863	0	0	0
T51	39767	0	0	0
T80	0	321	0	0
T81	0	421	0	0
T82	0	141	0	0
T83	0	281	0	0
T84	0	299	0	0
T85	0	200	0	0
T86	0	210	0	0
T87	657652	0	0	0
T88	27649	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468637740	5058	0	0
T18	412878	484	0	0
T19	184637	0	0	0
T28	14644	0	0	0
T29	5042	0	0	0
T31	0	315	0	0
T35	112139	0	0	0
T45	0	670	0	0
T49	318149	0	0	0
T50	47863	0	0	0
T51	39767	0	0	0
T80	0	317	0	0
T81	0	461	0	0
T82	0	168	0	0
T83	0	340	0	0
T84	0	429	0	0
T85	0	191	0	0
T86	0	187	0	0
T87	657652	0	0	0
T88	27649	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468637740	4335	0	0
T18	412878	436	0	0
T19	184637	0	0	0
T28	14644	0	0	0
T29	5042	0	0	0
T31	0	240	0	0
T35	112139	0	0	0
T45	0	451	0	0
T49	318149	0	0	0
T50	47863	0	0	0
T51	39767	0	0	0
T80	0	238	0	0
T81	0	535	0	0
T82	0	148	0	0
T83	0	346	0	0
T84	0	289	0	0
T85	0	225	0	0
T86	0	193	0	0
T87	657652	0	0	0
T88	27649	0	0	0