Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48650	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

374878

1

T1

13

T2

15

T3

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	106882	1			T1	1		T2	1		T3	1
values[0x0]	149713	1			T1	8		T2	10		T3	10
values[0x1]	166933	1			T1	9		T2	11		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29039	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

394489

1

T1

14

T2

19

T3

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1374	1			T5	2		T27	1		T217	1
valid_sources[0x01]	1894	1			T14	1		T15	13		T20	1
valid_sources[0x02]	1501	1			T27	1		T14	1		T15	5
valid_sources[0x03]	1574	1			T15	7		T20	4		T41	25
valid_sources[0x04]	1707	1			T1	1		T11	51		T217	1
valid_sources[0x05]	1494	1			T10	1		T15	15		T41	26
valid_sources[0x06]	1614	1			T11	8		T197	1		T15	7
valid_sources[0x07]	2017	1			T14	2		T15	28		T41	35
valid_sources[0x08]	1614	1			T3	1		T11	40		T33	1
valid_sources[0x09]	1592	1			T11	33		T217	1		T14	3
valid_sources[0x0a]	1450	1			T30	2		T14	21		T15	9
valid_sources[0x0b]	1783	1			T4	1		T8	1		T11	2
valid_sources[0x0c]	1957	1			T11	3		T15	18		T20	3
valid_sources[0x0d]	2064	1			T30	1		T14	23		T218	2
valid_sources[0x0e]	1424	1			T3	2		T11	6		T33	1
valid_sources[0x0f]	1958	1			T11	46		T30	1		T14	22
valid_sources[0x10]	1544	1			T1	1		T7	1		T11	49
valid_sources[0x11]	1636	1			T11	49		T14	10		T15	15
valid_sources[0x12]	1256	1			T6	1		T11	5		T14	23
valid_sources[0x13]	1609	1			T30	1		T15	24		T41	24
valid_sources[0x14]	1923	1			T3	2		T5	2		T7	1
valid_sources[0x15]	1839	1			T27	1		T15	17		T20	8
valid_sources[0x16]	2029	1			T6	1		T15	11		T41	26
valid_sources[0x17]	1338	1			T1	1		T11	1		T32	1
valid_sources[0x18]	1703	1			T14	8		T209	1		T15	14
valid_sources[0x19]	1732	1			T7	1		T11	19		T14	6
valid_sources[0x1a]	1694	1			T30	5		T207	2		T15	13
valid_sources[0x1b]	1686	1			T6	1		T9	1		T10	1
valid_sources[0x1c]	1223	1			T4	1		T7	1		T49	3
valid_sources[0x1d]	1737	1			T10	2		T11	8		T15	27
valid_sources[0x1e]	1823	1			T10	1		T11	12		T31	1
valid_sources[0x1f]	1770	1			T1	1		T8	1		T11	22
valid_sources[0x20]	2070	1			T8	3		T9	1		T10	1
valid_sources[0x21]	1343	1			T5	2		T8	1		T11	7
valid_sources[0x22]	2029	1			T11	3		T14	3		T15	8
valid_sources[0x23]	1934	1			T5	1		T10	1		T11	3
valid_sources[0x24]	1588	1			T4	2		T26	1		T49	1
valid_sources[0x25]	1442	1			T14	19		T15	11		T20	1
valid_sources[0x26]	1939	1			T11	16		T12	13		T15	8
valid_sources[0x27]	1431	1			T11	19		T15	14		T146	1
valid_sources[0x28]	1716	1			T11	27		T14	5		T219	1
valid_sources[0x29]	1369	1			T14	2		T219	1		T15	14
valid_sources[0x2a]	1616	1			T15	10		T20	4		T41	24
valid_sources[0x2b]	1526	1			T27	1		T14	7		T209	1
valid_sources[0x2c]	1999	1			T11	3		T170	1		T219	1
valid_sources[0x2d]	1460	1			T11	93		T27	1		T14	14
valid_sources[0x2e]	1601	1			T7	1		T11	8		T219	1
valid_sources[0x2f]	1505	1			T14	47		T211	1		T15	10
valid_sources[0x30]	1429	1			T1	1		T4	1		T26	1
valid_sources[0x31]	1790	1			T6	1		T9	1		T11	1
valid_sources[0x32]	1326	1			T11	8		T29	2		T14	5
valid_sources[0x33]	1864	1			T11	14		T14	6		T15	20
valid_sources[0x34]	1735	1			T14	1		T15	18		T41	18
valid_sources[0x35]	1651	1			T14	16		T15	7		T20	1
valid_sources[0x36]	1657	1			T11	6		T26	1		T27	1
valid_sources[0x37]	1493	1			T6	1		T11	42		T197	1
valid_sources[0x38]	1343	1			T1	1		T11	2		T14	3
valid_sources[0x39]	1511	1			T1	1		T15	12		T20	1
valid_sources[0x3a]	1462	1			T4	1		T11	34		T15	9
valid_sources[0x3b]	1588	1			T30	1		T32	1		T15	17
valid_sources[0x3c]	1356	1			T11	13		T14	32		T15	17
valid_sources[0x3d]	1549	1			T3	2		T26	1		T14	23
valid_sources[0x3e]	1288	1			T4	1		T9	1		T11	1
valid_sources[0x3f]	2070	1			T3	3		T33	1		T15	9
valid_sources[0x40]	1713	1			T197	3		T15	14		T20	5
valid_sources[0x41]	1316	1			T8	3		T9	1		T11	3
valid_sources[0x42]	1338	1			T11	8		T27	1		T14	9
valid_sources[0x43]	1175	1			T197	1		T15	8		T41	26
valid_sources[0x44]	1513	1			T9	1		T14	3		T15	6
valid_sources[0x45]	1739	1			T1	1		T11	30		T14	49
valid_sources[0x46]	1578	1			T1	1		T9	1		T11	2
valid_sources[0x47]	1832	1			T11	3		T48	22		T14	4
valid_sources[0x48]	1797	1			T3	2		T11	4		T15	12
valid_sources[0x49]	1794	1			T11	2		T27	1		T211	1
valid_sources[0x4a]	1229	1			T14	3		T209	2		T15	16
valid_sources[0x4b]	1162	1			T170	1		T14	30		T15	13
valid_sources[0x4c]	1300	1			T11	1		T218	4		T15	26
valid_sources[0x4d]	1937	1			T11	5		T14	12		T219	1
valid_sources[0x4e]	1686	1			T15	20		T220	1		T41	34
valid_sources[0x4f]	1669	1			T4	1		T11	3		T26	2
valid_sources[0x50]	1184	1			T11	10		T217	1		T211	3
valid_sources[0x51]	1404	1			T11	4		T14	18		T15	26
valid_sources[0x52]	1918	1			T1	1		T11	15		T217	1
valid_sources[0x53]	1648	1			T170	7		T14	12		T15	51
valid_sources[0x54]	1655	1			T11	20		T14	2		T209	2
valid_sources[0x55]	1599	1			T11	47		T15	5		T41	19
valid_sources[0x56]	2188	1			T7	1		T9	2		T14	26
valid_sources[0x57]	1645	1			T1	1		T27	2		T14	1
valid_sources[0x58]	1813	1			T4	1		T219	1		T15	7
valid_sources[0x59]	1176	1			T32	4		T49	1		T14	10
valid_sources[0x5a]	1768	1			T7	1		T29	3		T15	15
valid_sources[0x5b]	1422	1			T11	3		T26	1		T16	19
valid_sources[0x5c]	1748	1			T15	20		T146	1		T41	21
valid_sources[0x5d]	1568	1			T11	17		T28	22		T217	1
valid_sources[0x5e]	1880	1			T11	24		T14	1		T197	3
valid_sources[0x5f]	1507	1			T1	1		T33	2		T15	15
valid_sources[0x60]	2131	1			T9	2		T10	1		T11	9
valid_sources[0x61]	1450	1			T11	13		T211	1		T15	11
valid_sources[0x62]	1197	1			T2	22		T4	1		T8	1
valid_sources[0x63]	2022	1			T14	1		T209	2		T15	7
valid_sources[0x64]	1535	1			T11	2		T170	1		T14	18
valid_sources[0x65]	2042	1			T10	1		T14	8		T209	1
valid_sources[0x66]	1961	1			T14	2		T15	13		T221	3
valid_sources[0x67]	1785	1			T4	1		T11	24		T14	4
valid_sources[0x68]	1583	1			T11	6		T170	1		T14	4
valid_sources[0x69]	1428	1			T7	3		T11	8		T31	3
valid_sources[0x6a]	1380	1			T4	1		T11	3		T14	2
valid_sources[0x6b]	1388	1			T5	1		T32	2		T15	6
valid_sources[0x6c]	1726	1			T4	1		T11	1		T49	1
valid_sources[0x6d]	1781	1			T4	1		T14	6		T207	2
valid_sources[0x6e]	2019	1			T11	1		T14	19		T15	21
valid_sources[0x6f]	1810	1			T11	9		T27	1		T209	1
valid_sources[0x70]	1994	1			T11	9		T12	6		T15	43
valid_sources[0x71]	1699	1			T7	1		T8	1		T27	1
valid_sources[0x72]	1300	1			T11	5		T14	63		T197	1
valid_sources[0x73]	1712	1			T11	4		T31	2		T219	1
valid_sources[0x74]	1426	1			T26	1		T31	1		T15	11
valid_sources[0x75]	1564	1			T11	6		T26	1		T15	18
valid_sources[0x76]	1442	1			T7	1		T197	1		T15	15
valid_sources[0x77]	2491	1			T11	1		T27	1		T14	4
valid_sources[0x78]	1386	1			T10	2		T11	29		T14	4
valid_sources[0x79]	1533	1			T11	23		T49	1		T14	4
valid_sources[0x7a]	1566	1			T15	13		T41	20		T43	23
valid_sources[0x7b]	2170	1			T11	9		T15	16		T41	18
valid_sources[0x7c]	1608	1			T11	1		T15	16		T41	12
valid_sources[0x7d]	1384	1			T6	1		T31	5		T14	6
valid_sources[0x7e]	1912	1			T11	2		T15	16		T166	1
valid_sources[0x7f]	1698	1			T4	1		T11	5		T26	3
valid_sources[0x80]	1332	1			T11	2		T170	1		T217	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

92732

1

T1

1

T5

1

T6

1

values[0x0]

all_enables

biggest_size

141566

1

T1

6

T2

8

T3

8

values[0x1]

all_enables

biggest_size

140580

1

T1

6

T2

7

T3

5