Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	100.00	80.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	468181247	381244	0	0
wdog_bark_thold_rd_A	468181247	6532	0	0
wdog_bite_thold_rd_A	468181247	5594	0	0
wdog_ctrl_rd_A	468181247	5657	0	0
wdog_regwen_rd_A	468181247	6509	0	0
wkup_ctrl_rd_A	468181247	5639	0	0
wkup_thold_hi_rd_A	468181247	6220	0	0
wkup_thold_lo_rd_A	468181247	5498	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468181247	381244	0	0
T11	143837	1577	0	0
T12	18927	0	0	0
T13	13752	0	0	0
T14	0	1515	0	0
T15	0	2662	0	0
T17	114240	0	0	0
T23	54905	0	0	0
T26	56391	0	0	0
T27	43550	0	0	0
T28	45112	0	0	0
T29	13205	0	0	0
T30	10033	0	0	0
T41	0	4753	0	0
T42	0	1550	0	0
T43	0	4996	0	0
T44	0	8943	0	0
T45	0	2988	0	0
T46	0	3701	0	0
T47	0	5828	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468181247	6532	0	0
T43	236253	335	0	0
T44	332359	0	0	0
T45	175817	473	0	0
T47	0	781	0	0
T73	0	485	0	0
T74	0	138	0	0
T75	0	432	0	0
T76	0	470	0	0
T77	0	305	0	0
T78	0	387	0	0
T79	0	642	0	0
T80	46410	0	0	0
T81	50679	0	0	0
T82	39779	0	0	0
T83	16736	0	0	0
T84	10614	0	0	0
T85	115596	0	0	0
T86	11214	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468181247	5594	0	0
T43	236253	290	0	0
T44	332359	0	0	0
T45	175817	395	0	0
T47	0	660	0	0
T73	0	295	0	0
T74	0	93	0	0
T75	0	323	0	0
T76	0	384	0	0
T77	0	302	0	0
T78	0	348	0	0
T79	0	524	0	0
T80	46410	0	0	0
T81	50679	0	0	0
T82	39779	0	0	0
T83	16736	0	0	0
T84	10614	0	0	0
T85	115596	0	0	0
T86	11214	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468181247	5657	0	0
T43	236253	193	0	0
T44	332359	0	0	0
T45	175817	451	0	0
T47	0	612	0	0
T73	0	387	0	0
T74	0	98	0	0
T75	0	375	0	0
T76	0	447	0	0
T77	0	316	0	0
T78	0	300	0	0
T79	0	557	0	0
T80	46410	0	0	0
T81	50679	0	0	0
T82	39779	0	0	0
T83	16736	0	0	0
T84	10614	0	0	0
T85	115596	0	0	0
T86	11214	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468181247	6509	0	0
T43	236253	276	0	0
T44	332359	0	0	0
T45	175817	413	0	0
T47	0	660	0	0
T73	0	490	0	0
T74	0	110	0	0
T75	0	432	0	0
T76	0	501	0	0
T77	0	422	0	0
T78	0	445	0	0
T79	0	478	0	0
T80	46410	0	0	0
T81	50679	0	0	0
T82	39779	0	0	0
T83	16736	0	0	0
T84	10614	0	0	0
T85	115596	0	0	0
T86	11214	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468181247	5639	0	0
T43	236253	227	0	0
T44	332359	0	0	0
T45	175817	398	0	0
T47	0	599	0	0
T73	0	345	0	0
T74	0	132	0	0
T75	0	393	0	0
T76	0	347	0	0
T77	0	319	0	0
T78	0	323	0	0
T79	0	575	0	0
T80	46410	0	0	0
T81	50679	0	0	0
T82	39779	0	0	0
T83	16736	0	0	0
T84	10614	0	0	0
T85	115596	0	0	0
T86	11214	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468181247	6220	0	0
T43	236253	321	0	0
T44	332359	0	0	0
T45	175817	421	0	0
T47	0	707	0	0
T73	0	482	0	0
T74	0	140	0	0
T75	0	408	0	0
T76	0	474	0	0
T77	0	392	0	0
T78	0	463	0	0
T79	0	524	0	0
T80	46410	0	0	0
T81	50679	0	0	0
T82	39779	0	0	0
T83	16736	0	0	0
T84	10614	0	0	0
T85	115596	0	0	0
T86	11214	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468181247	5498	0	0
T43	236253	267	0	0
T44	332359	0	0	0
T45	175817	375	0	0
T47	0	611	0	0
T73	0	334	0	0
T74	0	170	0	0
T75	0	302	0	0
T76	0	342	0	0
T77	0	334	0	0
T78	0	278	0	0
T79	0	664	0	0
T80	46410	0	0	0
T81	50679	0	0	0
T82	39779	0	0	0
T83	16736	0	0	0
T84	10614	0	0	0
T85	115596	0	0	0
T86	11214	0	0	0