Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46320	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

358676

1

T1

14

T2

16

T3

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	102841	1			T1	1		T2	1		T3	1
values[0x0]	143487	1			T1	11		T2	13		T3	9
values[0x1]	158668	1			T1	6		T2	8		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27778	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

377218

1

T1

14

T2

17

T3

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1518	1			T22	16		T24	34		T36	5
valid_sources[0x01]	1552	1			T15	32		T22	21		T24	27
valid_sources[0x02]	1608	1			T4	2		T9	1		T15	6
valid_sources[0x03]	1622	1			T15	18		T22	15		T24	40
valid_sources[0x04]	1456	1			T15	9		T21	1		T177	1
valid_sources[0x05]	1348	1			T19	20		T22	34		T24	17
valid_sources[0x06]	1785	1			T15	1		T22	23		T24	13
valid_sources[0x07]	1301	1			T15	4		T35	1		T21	1
valid_sources[0x08]	1662	1			T15	25		T22	14		T24	29
valid_sources[0x09]	1436	1			T9	1		T23	22		T15	19
valid_sources[0x0a]	1656	1			T5	1		T15	4		T216	1
valid_sources[0x0b]	1849	1			T15	17		T177	1		T22	12
valid_sources[0x0c]	1571	1			T21	1		T22	28		T24	8
valid_sources[0x0d]	1401	1			T15	9		T22	13		T24	20
valid_sources[0x0e]	1575	1			T6	4		T15	1		T22	13
valid_sources[0x0f]	1797	1			T14	5		T15	35		T51	2
valid_sources[0x10]	1514	1			T2	1		T15	1		T22	24
valid_sources[0x11]	1615	1			T8	1		T15	9		T22	16
valid_sources[0x12]	1615	1			T8	2		T15	5		T84	1
valid_sources[0x13]	1568	1			T15	1		T22	18		T24	17
valid_sources[0x14]	1966	1			T15	23		T17	1		T197	1
valid_sources[0x15]	1763	1			T15	20		T22	14		T24	21
valid_sources[0x16]	1338	1			T15	16		T33	2		T197	1
valid_sources[0x17]	1425	1			T14	6		T15	2		T21	1
valid_sources[0x18]	1282	1			T15	21		T22	17		T24	28
valid_sources[0x19]	1349	1			T15	11		T35	1		T22	14
valid_sources[0x1a]	2057	1			T15	5		T216	1		T22	8
valid_sources[0x1b]	1262	1			T5	2		T15	5		T22	18
valid_sources[0x1c]	1865	1			T15	4		T22	19		T24	7
valid_sources[0x1d]	2200	1			T10	1		T15	3		T22	22
valid_sources[0x1e]	1758	1			T35	1		T22	21		T24	33
valid_sources[0x1f]	1378	1			T9	1		T15	6		T216	1
valid_sources[0x20]	1112	1			T15	3		T84	2		T22	14
valid_sources[0x21]	1913	1			T15	7		T21	2		T22	23
valid_sources[0x22]	1615	1			T15	43		T177	1		T22	15
valid_sources[0x23]	1834	1			T15	8		T35	1		T217	1
valid_sources[0x24]	1412	1			T15	18		T22	24		T24	25
valid_sources[0x25]	1515	1			T15	9		T21	1		T177	1
valid_sources[0x26]	1666	1			T10	1		T15	7		T22	28
valid_sources[0x27]	1884	1			T15	9		T21	1		T22	16
valid_sources[0x28]	1205	1			T9	1		T22	12		T24	22
valid_sources[0x29]	1559	1			T15	1		T22	24		T24	24
valid_sources[0x2a]	1509	1			T10	1		T15	12		T22	17
valid_sources[0x2b]	1498	1			T15	9		T18	1		T22	15
valid_sources[0x2c]	1593	1			T15	13		T18	1		T216	1
valid_sources[0x2d]	2010	1			T22	24		T24	34		T32	9
valid_sources[0x2e]	1551	1			T4	12		T15	3		T17	1
valid_sources[0x2f]	1976	1			T15	16		T177	1		T22	16
valid_sources[0x30]	1945	1			T10	1		T15	1		T22	27
valid_sources[0x31]	1683	1			T3	2		T15	10		T18	1
valid_sources[0x32]	1508	1			T21	1		T197	1		T22	23
valid_sources[0x33]	1811	1			T15	10		T22	21		T24	8
valid_sources[0x34]	1682	1			T15	4		T197	2		T22	15
valid_sources[0x35]	1289	1			T15	5		T31	19		T22	17
valid_sources[0x36]	1713	1			T10	1		T15	6		T34	22
valid_sources[0x37]	1668	1			T15	9		T22	21		T24	27
valid_sources[0x38]	1523	1			T5	1		T15	23		T22	15
valid_sources[0x39]	1960	1			T15	5		T22	21		T24	49
valid_sources[0x3a]	1775	1			T35	1		T216	1		T22	17
valid_sources[0x3b]	1250	1			T15	41		T20	2		T22	28
valid_sources[0x3c]	1387	1			T15	17		T177	1		T84	1
valid_sources[0x3d]	1644	1			T2	2		T15	2		T35	1
valid_sources[0x3e]	1425	1			T15	7		T18	1		T22	16
valid_sources[0x3f]	1506	1			T10	1		T15	6		T22	25
valid_sources[0x40]	1414	1			T211	20		T84	1		T22	26
valid_sources[0x41]	1987	1			T22	24		T24	27		T46	85
valid_sources[0x42]	1315	1			T15	2		T177	1		T22	18
valid_sources[0x43]	1370	1			T15	11		T22	20		T24	10
valid_sources[0x44]	1436	1			T15	15		T22	19		T24	14
valid_sources[0x45]	1287	1			T3	2		T15	17		T20	1
valid_sources[0x46]	1567	1			T22	11		T24	8		T26	1
valid_sources[0x47]	1816	1			T15	10		T22	19		T24	14
valid_sources[0x48]	1451	1			T35	1		T197	1		T22	17
valid_sources[0x49]	1621	1			T15	1		T22	13		T24	11
valid_sources[0x4a]	1543	1			T15	11		T22	13		T24	21
valid_sources[0x4b]	1713	1			T2	1		T6	1		T22	21
valid_sources[0x4c]	1574	1			T15	26		T22	21		T24	16
valid_sources[0x4d]	1347	1			T15	31		T22	15		T24	25
valid_sources[0x4e]	1555	1			T51	1		T22	19		T24	23
valid_sources[0x4f]	1228	1			T15	3		T22	24		T24	13
valid_sources[0x50]	1648	1			T15	2		T22	18		T24	26
valid_sources[0x51]	1586	1			T2	3		T15	2		T35	1
valid_sources[0x52]	1208	1			T8	2		T15	20		T22	11
valid_sources[0x53]	1651	1			T15	20		T22	21		T24	19
valid_sources[0x54]	1584	1			T15	2		T22	19		T24	19
valid_sources[0x55]	1349	1			T14	1		T15	11		T22	20
valid_sources[0x56]	1278	1			T15	2		T18	1		T22	10
valid_sources[0x57]	1482	1			T15	13		T177	1		T22	20
valid_sources[0x58]	1589	1			T6	3		T15	13		T18	1
valid_sources[0x59]	1435	1			T4	3		T15	6		T22	22
valid_sources[0x5a]	1786	1			T15	20		T18	1		T22	23
valid_sources[0x5b]	1379	1			T13	19		T15	6		T22	14
valid_sources[0x5c]	1282	1			T21	1		T22	24		T24	26
valid_sources[0x5d]	1975	1			T15	38		T35	1		T22	31
valid_sources[0x5e]	1759	1			T15	10		T22	12		T24	25
valid_sources[0x5f]	1507	1			T22	17		T24	21		T36	13
valid_sources[0x60]	1618	1			T15	32		T177	2		T22	11
valid_sources[0x61]	1295	1			T22	23		T24	17		T26	1
valid_sources[0x62]	1528	1			T22	20		T24	37		T196	1
valid_sources[0x63]	1268	1			T15	13		T22	17		T24	30
valid_sources[0x64]	1683	1			T15	1		T22	22		T24	24
valid_sources[0x65]	1418	1			T15	3		T84	1		T22	22
valid_sources[0x66]	1517	1			T8	3		T10	1		T15	1
valid_sources[0x67]	1704	1			T9	1		T51	1		T22	19
valid_sources[0x68]	2165	1			T15	1		T35	1		T216	1
valid_sources[0x69]	1640	1			T21	1		T22	15		T24	19
valid_sources[0x6a]	1847	1			T15	13		T51	1		T22	16
valid_sources[0x6b]	1719	1			T15	1		T216	1		T22	15
valid_sources[0x6c]	1575	1			T15	13		T22	21		T24	12
valid_sources[0x6d]	1527	1			T15	1		T35	1		T33	5
valid_sources[0x6e]	1609	1			T15	14		T35	1		T216	1
valid_sources[0x6f]	1554	1			T15	12		T22	24		T24	20
valid_sources[0x70]	1706	1			T15	2		T35	1		T22	21
valid_sources[0x71]	1824	1			T15	4		T22	16		T24	11
valid_sources[0x72]	1951	1			T7	273		T15	1		T51	1
valid_sources[0x73]	2006	1			T5	3		T15	7		T197	1
valid_sources[0x74]	1426	1			T15	4		T22	30		T24	27
valid_sources[0x75]	1661	1			T3	3		T15	4		T17	7
valid_sources[0x76]	1343	1			T2	1		T8	1		T22	20
valid_sources[0x77]	1427	1			T15	2		T16	19		T18	1
valid_sources[0x78]	1825	1			T15	2		T21	1		T22	21
valid_sources[0x79]	1370	1			T9	1		T15	7		T22	19
valid_sources[0x7a]	1270	1			T8	4		T15	6		T217	1
valid_sources[0x7b]	1297	1			T15	26		T22	9		T24	17
valid_sources[0x7c]	1151	1			T10	1		T15	10		T35	1
valid_sources[0x7d]	1307	1			T30	22		T15	4		T197	1
valid_sources[0x7e]	1715	1			T8	1		T15	3		T22	18
valid_sources[0x7f]	1549	1			T5	1		T22	15		T24	19
valid_sources[0x80]	1563	1			T3	15		T15	18		T21	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

88960

1

T4

1

T6

1

T7

13

values[0x0]

all_enables

biggest_size

135694

1

T1

9

T2

10

T3

6

values[0x1]

all_enables

biggest_size

134022

1

T1

5

T2

6

T3

8