Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	100.00	80.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	622911264	359210	0	0
wdog_bark_thold_rd_A	622911264	9959	0	0
wdog_bite_thold_rd_A	622911264	8922	0	0
wdog_ctrl_rd_A	622911264	8982	0	0
wdog_regwen_rd_A	622911264	10255	0	0
wkup_ctrl_rd_A	622911264	9071	0	0
wkup_thold_hi_rd_A	622911264	10273	0	0
wkup_thold_lo_rd_A	622911264	9285	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622911264	359210	0	0
T15	99802	1722	0	0
T16	11975	0	0	0
T17	12599	0	0	0
T18	9450	0	0	0
T19	299256	0	0	0
T22	0	5250	0	0
T24	0	4776	0	0
T25	108575	0	0	0
T28	245717	0	0	0
T34	25565	0	0	0
T35	56881	0	0	0
T36	0	2760	0	0
T37	0	10437	0	0
T46	0	4764	0	0
T47	0	1965	0	0
T48	0	7053	0	0
T49	0	8682	0	0
T50	0	6405	0	0
T51	56364	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622911264	9959	0	0
T15	99802	252	0	0
T16	11975	0	0	0
T17	12599	0	0	0
T18	9450	0	0	0
T19	299256	0	0	0
T24	0	513	0	0
T25	108575	0	0	0
T28	245717	0	0	0
T34	25565	0	0	0
T35	56881	0	0	0
T37	0	603	0	0
T47	0	157	0	0
T48	0	715	0	0
T51	56364	0	0	0
T79	0	309	0	0
T80	0	417	0	0
T81	0	720	0	0
T82	0	798	0	0
T83	0	302	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622911264	8922	0	0
T15	99802	249	0	0
T16	11975	0	0	0
T17	12599	0	0	0
T18	9450	0	0	0
T19	299256	0	0	0
T24	0	412	0	0
T25	108575	0	0	0
T28	245717	0	0	0
T34	25565	0	0	0
T35	56881	0	0	0
T37	0	553	0	0
T47	0	156	0	0
T48	0	585	0	0
T51	56364	0	0	0
T79	0	309	0	0
T80	0	355	0	0
T81	0	603	0	0
T82	0	671	0	0
T83	0	268	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622911264	8982	0	0
T15	99802	230	0	0
T16	11975	0	0	0
T17	12599	0	0	0
T18	9450	0	0	0
T19	299256	0	0	0
T24	0	492	0	0
T25	108575	0	0	0
T28	245717	0	0	0
T34	25565	0	0	0
T35	56881	0	0	0
T37	0	585	0	0
T47	0	122	0	0
T48	0	618	0	0
T51	56364	0	0	0
T79	0	301	0	0
T80	0	321	0	0
T81	0	552	0	0
T82	0	647	0	0
T83	0	282	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622911264	10255	0	0
T15	99802	229	0	0
T16	11975	0	0	0
T17	12599	0	0	0
T18	9450	0	0	0
T19	299256	0	0	0
T24	0	590	0	0
T25	108575	0	0	0
T28	245717	0	0	0
T34	25565	0	0	0
T35	56881	0	0	0
T37	0	698	0	0
T47	0	157	0	0
T48	0	745	0	0
T51	56364	0	0	0
T79	0	277	0	0
T80	0	317	0	0
T81	0	860	0	0
T82	0	873	0	0
T83	0	363	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622911264	9071	0	0
T15	99802	220	0	0
T16	11975	0	0	0
T17	12599	0	0	0
T18	9450	0	0	0
T19	299256	0	0	0
T24	0	435	0	0
T25	108575	0	0	0
T28	245717	0	0	0
T34	25565	0	0	0
T35	56881	0	0	0
T37	0	540	0	0
T47	0	133	0	0
T48	0	666	0	0
T51	56364	0	0	0
T79	0	290	0	0
T80	0	265	0	0
T81	0	713	0	0
T82	0	590	0	0
T83	0	279	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622911264	10273	0	0
T15	99802	244	0	0
T16	11975	0	0	0
T17	12599	0	0	0
T18	9450	0	0	0
T19	299256	0	0	0
T24	0	574	0	0
T25	108575	0	0	0
T28	245717	0	0	0
T34	25565	0	0	0
T35	56881	0	0	0
T37	0	520	0	0
T47	0	181	0	0
T48	0	878	0	0
T51	56364	0	0	0
T79	0	407	0	0
T80	0	445	0	0
T81	0	760	0	0
T82	0	843	0	0
T83	0	304	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622911264	9285	0	0
T15	99802	234	0	0
T16	11975	0	0	0
T17	12599	0	0	0
T18	9450	0	0	0
T19	299256	0	0	0
T24	0	466	0	0
T25	108575	0	0	0
T28	245717	0	0	0
T34	25565	0	0	0
T35	56881	0	0	0
T37	0	605	0	0
T47	0	116	0	0
T48	0	649	0	0
T51	56364	0	0	0
T79	0	296	0	0
T80	0	339	0	0
T81	0	736	0	0
T82	0	796	0	0
T83	0	307	0	0