Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37482	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

275139

1

T1

13

T2

13

T3

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	79383	1			T1	1		T2	1		T3	1
values[0x0]	110890	1			T1	8		T2	9		T3	9
values[0x1]	122348	1			T1	10		T2	12		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	22931	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

289690

1

T1

15

T2

14

T3

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1148	1			T6	1		T20	13		T21	8
valid_sources[0x01]	1509	1			T4	4		T20	17		T21	9
valid_sources[0x02]	1258	1			T20	7		T21	12		T22	7
valid_sources[0x03]	1196	1			T20	16		T35	1		T21	9
valid_sources[0x04]	1147	1			T20	15		T21	6		T22	8
valid_sources[0x05]	1049	1			T174	1		T21	12		T22	9
valid_sources[0x06]	1382	1			T20	7		T21	17		T53	1
valid_sources[0x07]	1487	1			T20	8		T21	8		T22	7
valid_sources[0x08]	1015	1			T16	1		T20	7		T21	14
valid_sources[0x09]	1180	1			T8	15		T16	1		T19	1
valid_sources[0x0a]	1166	1			T19	1		T20	18		T21	16
valid_sources[0x0b]	1008	1			T174	1		T20	13		T21	7
valid_sources[0x0c]	1083	1			T174	1		T20	25		T21	13
valid_sources[0x0d]	1121	1			T9	9		T20	1		T21	12
valid_sources[0x0e]	1228	1			T20	4		T21	14		T53	3
valid_sources[0x0f]	1585	1			T16	1		T20	3		T21	8
valid_sources[0x10]	1143	1			T24	1		T20	24		T21	11
valid_sources[0x11]	1121	1			T3	1		T20	5		T21	7
valid_sources[0x12]	1160	1			T174	2		T20	12		T21	6
valid_sources[0x13]	1595	1			T3	1		T13	9		T20	8
valid_sources[0x14]	1175	1			T20	1		T21	5		T22	3
valid_sources[0x15]	1501	1			T20	9		T21	10		T22	11
valid_sources[0x16]	1405	1			T174	1		T20	8		T21	8
valid_sources[0x17]	1250	1			T6	1		T21	3		T52	1
valid_sources[0x18]	901	1			T174	1		T20	18		T21	4
valid_sources[0x19]	988	1			T20	4		T21	12		T22	10
valid_sources[0x1a]	1060	1			T24	1		T20	20		T21	8
valid_sources[0x1b]	1097	1			T20	6		T21	13		T22	4
valid_sources[0x1c]	934	1			T6	2		T24	1		T20	9
valid_sources[0x1d]	1326	1			T9	1		T33	1		T20	20
valid_sources[0x1e]	1127	1			T5	1		T33	1		T21	6
valid_sources[0x1f]	1005	1			T20	12		T21	16		T53	1
valid_sources[0x20]	1012	1			T20	3		T21	11		T22	5
valid_sources[0x21]	1125	1			T4	1		T20	8		T35	1
valid_sources[0x22]	1319	1			T16	1		T20	17		T21	10
valid_sources[0x23]	1221	1			T33	3		T20	29		T21	4
valid_sources[0x24]	998	1			T20	13		T21	9		T188	1
valid_sources[0x25]	1238	1			T8	7		T19	1		T20	1
valid_sources[0x26]	979	1			T16	2		T20	11		T21	3
valid_sources[0x27]	1304	1			T20	12		T21	12		T22	2
valid_sources[0x28]	1175	1			T12	1		T33	2		T20	1
valid_sources[0x29]	1273	1			T20	3		T21	2		T22	12
valid_sources[0x2a]	1510	1			T20	22		T21	12		T22	2
valid_sources[0x2b]	1388	1			T20	10		T21	8		T22	7
valid_sources[0x2c]	1153	1			T174	1		T20	7		T21	10
valid_sources[0x2d]	1629	1			T21	11		T201	1		T43	28
valid_sources[0x2e]	1111	1			T24	1		T20	22		T21	7
valid_sources[0x2f]	1075	1			T12	1		T20	4		T21	6
valid_sources[0x30]	1446	1			T20	2		T21	10		T22	11
valid_sources[0x31]	1509	1			T24	1		T20	13		T21	8
valid_sources[0x32]	1524	1			T4	1		T20	9		T21	11
valid_sources[0x33]	1210	1			T20	3		T21	13		T22	7
valid_sources[0x34]	1120	1			T20	3		T21	8		T191	2
valid_sources[0x35]	989	1			T7	22		T20	29		T21	3
valid_sources[0x36]	1167	1			T20	28		T21	4		T204	2
valid_sources[0x37]	1272	1			T20	7		T35	1		T21	2
valid_sources[0x38]	1632	1			T20	2		T21	5		T22	5
valid_sources[0x39]	970	1			T20	1		T35	1		T21	10
valid_sources[0x3a]	1412	1			T3	1		T16	1		T35	1
valid_sources[0x3b]	1084	1			T17	19		T21	11		T22	2
valid_sources[0x3c]	1403	1			T20	20		T21	14		T43	17
valid_sources[0x3d]	1288	1			T4	1		T20	17		T21	8
valid_sources[0x3e]	1009	1			T19	1		T21	6		T201	1
valid_sources[0x3f]	1394	1			T4	2		T19	1		T20	11
valid_sources[0x40]	1301	1			T21	5		T22	11		T43	18
valid_sources[0x41]	1161	1			T24	1		T20	22		T21	15
valid_sources[0x42]	959	1			T20	10		T21	16		T191	1
valid_sources[0x43]	1207	1			T20	7		T21	13		T22	4
valid_sources[0x44]	1262	1			T3	1		T6	1		T9	1
valid_sources[0x45]	1071	1			T16	1		T20	2		T21	9
valid_sources[0x46]	1084	1			T20	11		T21	6		T22	2
valid_sources[0x47]	1109	1			T21	5		T22	6		T43	16
valid_sources[0x48]	1126	1			T174	1		T19	1		T20	10
valid_sources[0x49]	1217	1			T12	1		T20	3		T21	10
valid_sources[0x4a]	1176	1			T3	1		T20	12		T21	9
valid_sources[0x4b]	1193	1			T5	1		T20	1		T21	12
valid_sources[0x4c]	1140	1			T12	1		T20	8		T21	2
valid_sources[0x4d]	1100	1			T21	4		T22	1		T43	6
valid_sources[0x4e]	1218	1			T6	1		T20	14		T21	3
valid_sources[0x4f]	1131	1			T23	22		T20	8		T35	1
valid_sources[0x50]	1215	1			T16	2		T20	16		T21	2
valid_sources[0x51]	1271	1			T10	1		T20	18		T21	13
valid_sources[0x52]	1095	1			T10	1		T24	1		T13	10
valid_sources[0x53]	1347	1			T24	1		T20	15		T35	1
valid_sources[0x54]	1140	1			T2	3		T21	21		T22	3
valid_sources[0x55]	1034	1			T19	1		T20	2		T21	17
valid_sources[0x56]	1326	1			T5	6		T20	2		T21	2
valid_sources[0x57]	1118	1			T24	2		T16	1		T20	28
valid_sources[0x58]	1082	1			T20	1		T21	3		T22	4
valid_sources[0x59]	1035	1			T20	34		T21	10		T22	2
valid_sources[0x5a]	1276	1			T6	1		T20	12		T21	6
valid_sources[0x5b]	1311	1			T4	1		T12	1		T16	1
valid_sources[0x5c]	1232	1			T24	1		T20	12		T21	10
valid_sources[0x5d]	1480	1			T9	1		T10	1		T20	6
valid_sources[0x5e]	1243	1			T20	12		T21	6		T22	2
valid_sources[0x5f]	1628	1			T12	1		T20	5		T21	17
valid_sources[0x60]	1367	1			T24	1		T20	23		T21	11
valid_sources[0x61]	976	1			T20	7		T21	16		T188	1
valid_sources[0x62]	1399	1			T20	3		T21	18		T22	2
valid_sources[0x63]	1050	1			T20	8		T21	15		T49	3
valid_sources[0x64]	1192	1			T5	2		T20	8		T21	2
valid_sources[0x65]	1214	1			T4	2		T10	1		T35	1
valid_sources[0x66]	1278	1			T14	4		T20	8		T21	6
valid_sources[0x67]	1674	1			T20	2		T21	7		T22	4
valid_sources[0x68]	1205	1			T20	14		T21	7		T43	11
valid_sources[0x69]	979	1			T20	2		T21	1		T22	9
valid_sources[0x6a]	1333	1			T20	11		T21	7		T22	5
valid_sources[0x6b]	1173	1			T20	1		T21	15		T22	6
valid_sources[0x6c]	1221	1			T20	3		T21	13		T22	7
valid_sources[0x6d]	1484	1			T20	11		T21	8		T22	3
valid_sources[0x6e]	1306	1			T10	2		T20	20		T21	7
valid_sources[0x6f]	1245	1			T20	4		T21	9		T22	7
valid_sources[0x70]	1174	1			T16	1		T20	10		T35	1
valid_sources[0x71]	1106	1			T24	1		T20	1		T21	20
valid_sources[0x72]	1274	1			T33	1		T20	4		T21	10
valid_sources[0x73]	1278	1			T19	1		T20	15		T21	10
valid_sources[0x74]	1352	1			T20	9		T21	11		T191	1
valid_sources[0x75]	1282	1			T20	5		T21	10		T22	5
valid_sources[0x76]	1204	1			T20	5		T21	4		T22	9
valid_sources[0x77]	1170	1			T20	7		T21	5		T53	1
valid_sources[0x78]	1159	1			T35	1		T21	16		T22	2
valid_sources[0x79]	1147	1			T20	4		T21	7		T22	8
valid_sources[0x7a]	1165	1			T20	1		T21	6		T22	5
valid_sources[0x7b]	1310	1			T20	4		T35	1		T21	12
valid_sources[0x7c]	1326	1			T20	7		T21	9		T22	9
valid_sources[0x7d]	1317	1			T6	1		T20	7		T21	16
valid_sources[0x7e]	1347	1			T12	1		T20	9		T21	6
valid_sources[0x7f]	1644	1			T12	1		T20	17		T21	5
valid_sources[0x80]	1168	1			T21	10		T22	5		T43	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

67823

1

T3

1

T5

1

T6

1

values[0x0]

all_enables

biggest_size

104121

1

T1

8

T2

6

T3

5

values[0x1]

all_enables

biggest_size

103195

1

T1

5

T2

7

T3

6