Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42856	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

320412

1

T1

13

T2

13

T3

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	92623	1			T1	1		T2	1		T3	1
values[0x0]	127770	1			T1	6		T2	7		T3	10
values[0x1]	142875	1			T1	11		T2	11		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25815	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

337453

1

T1

14

T2

14

T3

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1376	1			T18	16		T20	14		T49	1
valid_sources[0x01]	1591	1			T13	1		T18	8		T20	7
valid_sources[0x02]	2341	1			T18	1		T20	15		T31	49
valid_sources[0x03]	1513	1			T10	2		T18	13		T20	23
valid_sources[0x04]	1626	1			T17	1		T18	1		T20	10
valid_sources[0x05]	1060	1			T12	1		T18	14		T20	17
valid_sources[0x06]	926	1			T9	1		T21	1		T17	1
valid_sources[0x07]	1475	1			T12	1		T18	11		T20	8
valid_sources[0x08]	1259	1			T18	50		T19	6		T20	11
valid_sources[0x09]	1359	1			T18	4		T19	5		T20	17
valid_sources[0x0a]	1272	1			T10	1		T18	24		T19	2
valid_sources[0x0b]	1487	1			T18	15		T20	12		T25	3
valid_sources[0x0c]	1278	1			T4	2		T20	10		T25	7
valid_sources[0x0d]	1040	1			T30	8		T18	18		T20	11
valid_sources[0x0e]	1553	1			T12	1		T18	9		T19	8
valid_sources[0x0f]	1469	1			T9	1		T18	27		T20	14
valid_sources[0x10]	1389	1			T20	30		T40	33		T41	8
valid_sources[0x11]	1006	1			T8	1		T9	1		T18	16
valid_sources[0x12]	1418	1			T21	1		T20	7		T31	118
valid_sources[0x13]	1201	1			T12	1		T13	1		T20	21
valid_sources[0x14]	1254	1			T12	1		T157	3		T18	25
valid_sources[0x15]	1404	1			T9	2		T157	2		T18	3
valid_sources[0x16]	1233	1			T2	1		T18	6		T20	8
valid_sources[0x17]	1513	1			T8	2		T15	1		T20	6
valid_sources[0x18]	1289	1			T18	40		T19	12		T20	14
valid_sources[0x19]	1406	1			T9	1		T18	19		T19	4
valid_sources[0x1a]	1555	1			T10	1		T18	7		T20	5
valid_sources[0x1b]	1703	1			T18	13		T45	3		T19	5
valid_sources[0x1c]	1144	1			T18	10		T19	13		T20	17
valid_sources[0x1d]	1703	1			T18	26		T20	3		T25	2
valid_sources[0x1e]	1865	1			T13	2		T18	16		T20	20
valid_sources[0x1f]	1212	1			T18	8		T19	1		T20	14
valid_sources[0x20]	1176	1			T21	1		T18	1		T19	2
valid_sources[0x21]	1396	1			T18	7		T20	9		T82	1
valid_sources[0x22]	976	1			T18	3		T19	6		T20	7
valid_sources[0x23]	1702	1			T10	1		T18	3		T19	2
valid_sources[0x24]	840	1			T5	1		T13	1		T18	6
valid_sources[0x25]	1505	1			T8	1		T18	20		T20	16
valid_sources[0x26]	1367	1			T18	40		T19	3		T20	12
valid_sources[0x27]	1805	1			T18	9		T46	2		T47	6
valid_sources[0x28]	1964	1			T9	1		T13	2		T18	4
valid_sources[0x29]	1214	1			T10	1		T18	9		T20	14
valid_sources[0x2a]	1013	1			T5	1		T10	1		T18	12
valid_sources[0x2b]	1181	1			T8	1		T18	1		T20	9
valid_sources[0x2c]	1219	1			T7	6		T18	37		T20	10
valid_sources[0x2d]	1091	1			T20	11		T25	1		T84	1
valid_sources[0x2e]	951	1			T30	14		T18	6		T19	6
valid_sources[0x2f]	1090	1			T19	1		T20	10		T75	1
valid_sources[0x30]	1611	1			T16	2		T20	13		T24	184
valid_sources[0x31]	1317	1			T18	10		T19	4		T20	15
valid_sources[0x32]	1757	1			T15	1		T18	33		T19	3
valid_sources[0x33]	1668	1			T18	9		T45	2		T20	13
valid_sources[0x34]	1246	1			T7	2		T18	20		T19	4
valid_sources[0x35]	1135	1			T9	1		T10	1		T20	7
valid_sources[0x36]	1884	1			T12	1		T18	7		T45	1
valid_sources[0x37]	1466	1			T18	4		T20	10		T25	6
valid_sources[0x38]	1482	1			T8	1		T19	7		T20	16
valid_sources[0x39]	1909	1			T2	1		T8	3		T10	1
valid_sources[0x3a]	1370	1			T17	1		T18	21		T29	1
valid_sources[0x3b]	1270	1			T7	2		T18	13		T19	4
valid_sources[0x3c]	1115	1			T18	7		T19	2		T20	6
valid_sources[0x3d]	1768	1			T18	5		T20	27		T48	1
valid_sources[0x3e]	1579	1			T18	25		T20	15		T83	1
valid_sources[0x3f]	1502	1			T4	4		T21	1		T18	10
valid_sources[0x40]	1462	1			T18	1		T20	20		T83	2
valid_sources[0x41]	1560	1			T5	1		T12	1		T15	2
valid_sources[0x42]	1324	1			T18	11		T20	7		T25	1
valid_sources[0x43]	1628	1			T18	5		T19	1		T20	11
valid_sources[0x44]	1752	1			T2	1		T12	1		T18	2
valid_sources[0x45]	1429	1			T5	1		T13	1		T18	12
valid_sources[0x46]	1407	1			T157	1		T18	17		T19	8
valid_sources[0x47]	1565	1			T18	31		T20	11		T24	1
valid_sources[0x48]	1149	1			T18	4		T20	8		T31	44
valid_sources[0x49]	1603	1			T21	1		T18	9		T20	16
valid_sources[0x4a]	1274	1			T15	1		T18	17		T20	15
valid_sources[0x4b]	1819	1			T2	1		T5	1		T18	13
valid_sources[0x4c]	1674	1			T18	3		T20	10		T25	1
valid_sources[0x4d]	1120	1			T20	25		T25	1		T24	9
valid_sources[0x4e]	1375	1			T10	1		T18	8		T20	15
valid_sources[0x4f]	1388	1			T12	1		T18	15		T19	4
valid_sources[0x50]	1617	1			T18	1		T20	31		T31	2
valid_sources[0x51]	1170	1			T18	1		T20	10		T210	1
valid_sources[0x52]	1269	1			T16	1		T18	8		T19	2
valid_sources[0x53]	1951	1			T2	1		T18	40		T20	16
valid_sources[0x54]	1114	1			T4	3		T18	4		T20	20
valid_sources[0x55]	1695	1			T18	13		T47	6		T20	24
valid_sources[0x56]	1334	1			T12	1		T19	5		T20	9
valid_sources[0x57]	2099	1			T5	1		T20	22		T24	1
valid_sources[0x58]	1401	1			T16	1		T18	18		T19	1
valid_sources[0x59]	1794	1			T18	9		T19	1		T20	24
valid_sources[0x5a]	1298	1			T2	1		T5	1		T10	1
valid_sources[0x5b]	1672	1			T12	1		T157	1		T18	1
valid_sources[0x5c]	1514	1			T157	1		T20	25		T25	1
valid_sources[0x5d]	1202	1			T8	1		T17	1		T18	3
valid_sources[0x5e]	1468	1			T20	19		T82	1		T24	102
valid_sources[0x5f]	1614	1			T2	1		T14	22		T21	1
valid_sources[0x60]	1437	1			T12	1		T21	1		T17	1
valid_sources[0x61]	1085	1			T18	30		T20	24		T25	1
valid_sources[0x62]	1484	1			T13	1		T16	1		T157	2
valid_sources[0x63]	1365	1			T5	1		T7	3		T18	23
valid_sources[0x64]	1009	1			T7	2		T10	1		T18	5
valid_sources[0x65]	1583	1			T18	14		T20	7		T83	1
valid_sources[0x66]	1392	1			T4	3		T21	1		T18	22
valid_sources[0x67]	1956	1			T18	5		T20	23		T40	20
valid_sources[0x68]	1673	1			T10	1		T19	3		T20	9
valid_sources[0x69]	1259	1			T21	1		T18	14		T20	18
valid_sources[0x6a]	1919	1			T13	1		T18	32		T19	2
valid_sources[0x6b]	1612	1			T18	1		T19	3		T20	7
valid_sources[0x6c]	1286	1			T8	1		T9	2		T17	3
valid_sources[0x6d]	1787	1			T9	1		T21	2		T18	18
valid_sources[0x6e]	1443	1			T45	3		T19	5		T20	7
valid_sources[0x6f]	1258	1			T18	2		T19	1		T20	17
valid_sources[0x70]	1950	1			T18	3		T20	21		T25	3
valid_sources[0x71]	1269	1			T46	3		T20	7		T25	1
valid_sources[0x72]	1141	1			T157	1		T18	22		T20	16
valid_sources[0x73]	1724	1			T18	32		T19	6		T20	20
valid_sources[0x74]	887	1			T2	1		T10	1		T20	10
valid_sources[0x75]	1154	1			T12	1		T157	1		T18	64
valid_sources[0x76]	1104	1			T18	1		T20	7		T24	26
valid_sources[0x77]	1298	1			T7	1		T13	2		T18	2
valid_sources[0x78]	1227	1			T18	4		T20	7		T41	10
valid_sources[0x79]	1429	1			T12	2		T157	1		T18	21
valid_sources[0x7a]	1462	1			T18	20		T20	24		T31	48
valid_sources[0x7b]	2306	1			T18	21		T20	25		T25	1
valid_sources[0x7c]	1683	1			T18	18		T19	1		T20	11
valid_sources[0x7d]	1149	1			T10	1		T18	11		T46	1
valid_sources[0x7e]	1518	1			T8	1		T18	18		T20	10
valid_sources[0x7f]	1748	1			T2	1		T10	1		T18	19
valid_sources[0x80]	1423	1			T18	7		T20	16		T82	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

79730

1

T1

1

T6

1

T9

1

values[0x0]

all_enables

biggest_size

120571

1

T1

6

T2

5

T3

9

values[0x1]

all_enables

biggest_size

120111

1

T1

6

T2

8

T3

6