Module Definition
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Module : prim_lc_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_lc_sync_escalate_en 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_sync_escalate_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.00 100.00 80.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_lc_sync
Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00

67 always_ff @(posedge clk_i) begin 68 1/1 lc_en_in_sva_q <= lc_en_i; Tests: T1 T2 T3  69 end 70 `ASSERT(OutputDelay_A, 71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} || 72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1))) 73 `endif 74 end else begin : gen_no_flops 75 //VCS coverage off 76 // pragma coverage off 77 78 // This unused companion logic helps remove lint errors 79 // for modules where clock and reset are used for assertions only 80 // or nothing at all. 81 // This logic will be removed for sythesis since it is unloaded. 82 lc_ctrl_pkg::lc_tx_t unused_logic; 83 always_ff @(posedge clk_i or negedge rst_ni) begin 84 if (!rst_ni) begin 85 unused_logic <= lc_ctrl_pkg::Off; 86 end else begin 87 unused_logic <= lc_en_i; 88 end 89 end 90 //VCS coverage on 91 // pragma coverage on 92 93 assign lc_en = lc_en_i; 94 95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}}) 96 end 97 98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out; 100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 101 prim_sec_anchor_buf u_prim_buf ( 102 .in_i(lc_en[k]), 103 .out_o(lc_en_out[k]) 104 ); 105 end 106 3/3 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T6 T11 T22  | T6 T11 T22  | T6 T11 T22 

Assert Coverage for Module : prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 250 250 0 0
OutputsKnown_A 2368818 2311971 0 0
gen_flops.OutputDelay_A 2368818 2309089 0 732


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 250 250 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T11 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2368818 2311971 0 0
T1 96 28 0 0
T2 95 21 0 0
T3 90 23 0 0
T4 102 16 0 0
T5 115 18 0 0
T6 126 37 0 0
T7 81 23 0 0
T8 84 20 0 0
T9 121 21 0 0
T11 842 16 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2368818 2309089 0 732
T1 96 25 0 3
T2 95 18 0 3
T3 90 20 0 3
T4 102 13 0 3
T5 115 15 0 3
T6 126 34 0 3
T7 81 20 0 3
T8 84 17 0 3
T9 121 18 0 3
T11 842 4 0 3