Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	100.00	80.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	600234759	322357	0	0
wdog_bark_thold_rd_A	600234759	6423	0	0
wdog_bite_thold_rd_A	600234759	6252	0	0
wdog_ctrl_rd_A	600234759	5876	0	0
wdog_regwen_rd_A	600234759	6973	0	0
wkup_ctrl_rd_A	600234759	5723	0	0
wkup_thold_hi_rd_A	600234759	6481	0	0
wkup_thold_lo_rd_A	600234759	5855	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600234759	322357	0	0
T18	188165	2455	0	0
T19	103983	0	0	0
T20	229110	4977	0	0
T24	0	1846	0	0
T28	756660	0	0	0
T29	41972	0	0	0
T31	0	4498	0	0
T32	0	11631	0	0
T40	0	4379	0	0
T41	0	1880	0	0
T42	0	8518	0	0
T43	0	9441	0	0
T44	0	12416	0	0
T45	54237	0	0	0
T46	13350	0	0	0
T47	102546	0	0	0
T48	13736	0	0	0
T49	758133	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600234759	6423	0	0
T20	229110	402	0	0
T24	145437	315	0	0
T25	113384	0	0	0
T26	323259	0	0	0
T31	173776	0	0	0
T33	0	1092	0	0
T41	0	296	0	0
T48	13736	0	0	0
T49	758133	0	0	0
T76	0	339	0	0
T77	0	94	0	0
T78	0	245	0	0
T79	0	192	0	0
T80	0	584	0	0
T81	0	319	0	0
T82	777922	0	0	0
T83	914039	0	0	0
T84	663710	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600234759	6252	0	0
T20	229110	452	0	0
T24	145437	222	0	0
T25	113384	0	0	0
T26	323259	0	0	0
T31	173776	0	0	0
T33	0	1299	0	0
T41	0	189	0	0
T48	13736	0	0	0
T49	758133	0	0	0
T76	0	334	0	0
T77	0	70	0	0
T78	0	261	0	0
T79	0	273	0	0
T80	0	514	0	0
T81	0	274	0	0
T82	777922	0	0	0
T83	914039	0	0	0
T84	663710	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600234759	5876	0	0
T20	229110	290	0	0
T24	145437	363	0	0
T25	113384	0	0	0
T26	323259	0	0	0
T31	173776	0	0	0
T33	0	1011	0	0
T41	0	160	0	0
T48	13736	0	0	0
T49	758133	0	0	0
T76	0	345	0	0
T77	0	72	0	0
T78	0	257	0	0
T79	0	293	0	0
T80	0	408	0	0
T81	0	296	0	0
T82	777922	0	0	0
T83	914039	0	0	0
T84	663710	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600234759	6973	0	0
T20	229110	458	0	0
T24	145437	264	0	0
T25	113384	0	0	0
T26	323259	0	0	0
T31	173776	0	0	0
T33	0	1229	0	0
T41	0	203	0	0
T48	13736	0	0	0
T49	758133	0	0	0
T76	0	326	0	0
T77	0	96	0	0
T78	0	385	0	0
T79	0	282	0	0
T80	0	653	0	0
T81	0	333	0	0
T82	777922	0	0	0
T83	914039	0	0	0
T84	663710	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600234759	5723	0	0
T20	229110	278	0	0
T24	145437	246	0	0
T25	113384	0	0	0
T26	323259	0	0	0
T31	173776	0	0	0
T33	0	1155	0	0
T41	0	193	0	0
T48	13736	0	0	0
T49	758133	0	0	0
T76	0	281	0	0
T77	0	114	0	0
T78	0	244	0	0
T79	0	253	0	0
T80	0	417	0	0
T81	0	293	0	0
T82	777922	0	0	0
T83	914039	0	0	0
T84	663710	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600234759	6481	0	0
T20	229110	380	0	0
T24	145437	248	0	0
T25	113384	0	0	0
T26	323259	0	0	0
T31	173776	0	0	0
T33	0	1306	0	0
T41	0	295	0	0
T48	13736	0	0	0
T49	758133	0	0	0
T76	0	315	0	0
T77	0	78	0	0
T78	0	288	0	0
T79	0	238	0	0
T80	0	657	0	0
T81	0	327	0	0
T82	777922	0	0	0
T83	914039	0	0	0
T84	663710	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	600234759	5855	0	0
T20	229110	436	0	0
T24	145437	310	0	0
T25	113384	0	0	0
T26	323259	0	0	0
T31	173776	0	0	0
T33	0	1101	0	0
T41	0	158	0	0
T48	13736	0	0	0
T49	758133	0	0	0
T76	0	242	0	0
T77	0	71	0	0
T78	0	196	0	0
T79	0	300	0	0
T80	0	531	0	0
T81	0	293	0	0
T82	777922	0	0	0
T83	914039	0	0	0
T84	663710	0	0	0