Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36254	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

260773

1

T1

15

T2

12

T3

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	75530	1			T1	1		T2	1		T3	1
values[0x0]	105055	1			T1	8		T2	9		T3	10
values[0x1]	116442	1			T1	13		T2	8		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	22453	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

274574

1

T1

17

T2

13

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1230	1			T7	1		T15	23		T16	34
valid_sources[0x01]	983	1			T15	25		T16	34		T27	26
valid_sources[0x02]	995	1			T15	28		T16	26		T27	21
valid_sources[0x03]	1445	1			T10	242		T19	2		T15	25
valid_sources[0x04]	1187	1			T15	22		T16	35		T27	21
valid_sources[0x05]	846	1			T9	1		T15	22		T16	23
valid_sources[0x06]	1027	1			T15	17		T16	40		T41	1
valid_sources[0x07]	957	1			T10	4		T15	35		T16	36
valid_sources[0x08]	1116	1			T6	1		T10	96		T15	14
valid_sources[0x09]	1404	1			T7	1		T10	183		T15	29
valid_sources[0x0a]	812	1			T2	2		T15	16		T16	35
valid_sources[0x0b]	1076	1			T10	115		T15	25		T16	24
valid_sources[0x0c]	1111	1			T15	27		T16	31		T26	2
valid_sources[0x0d]	869	1			T15	29		T16	36		T27	18
valid_sources[0x0e]	1200	1			T15	27		T16	30		T27	18
valid_sources[0x0f]	1080	1			T15	24		T16	30		T27	12
valid_sources[0x10]	1309	1			T10	4		T15	16		T16	43
valid_sources[0x11]	949	1			T15	24		T16	29		T26	1
valid_sources[0x12]	927	1			T6	1		T15	18		T16	37
valid_sources[0x13]	1141	1			T10	141		T15	25		T16	39
valid_sources[0x14]	1002	1			T10	73		T15	20		T16	26
valid_sources[0x15]	1287	1			T10	55		T15	34		T16	35
valid_sources[0x16]	877	1			T15	17		T16	38		T27	17
valid_sources[0x17]	1051	1			T15	25		T16	39		T27	17
valid_sources[0x18]	1300	1			T10	177		T15	19		T16	32
valid_sources[0x19]	1100	1			T10	94		T15	35		T16	32
valid_sources[0x1a]	908	1			T7	2		T15	20		T16	38
valid_sources[0x1b]	1330	1			T15	21		T16	42		T27	19
valid_sources[0x1c]	1007	1			T15	16		T16	37		T27	15
valid_sources[0x1d]	1597	1			T15	14		T16	34		T17	2
valid_sources[0x1e]	1116	1			T15	25		T16	41		T27	19
valid_sources[0x1f]	1115	1			T15	24		T16	29		T27	28
valid_sources[0x20]	1251	1			T4	22		T10	154		T15	20
valid_sources[0x21]	1050	1			T15	22		T16	54		T27	12
valid_sources[0x22]	1383	1			T10	99		T15	15		T16	29
valid_sources[0x23]	1435	1			T13	6		T15	22		T16	30
valid_sources[0x24]	1440	1			T15	21		T16	41		T27	23
valid_sources[0x25]	950	1			T2	3		T15	26		T16	38
valid_sources[0x26]	1163	1			T10	153		T15	13		T16	36
valid_sources[0x27]	1452	1			T15	16		T16	35		T27	17
valid_sources[0x28]	1735	1			T10	15		T15	20		T16	35
valid_sources[0x29]	1433	1			T15	16		T16	33		T27	16
valid_sources[0x2a]	1023	1			T10	3		T15	5		T16	41
valid_sources[0x2b]	1643	1			T10	6		T15	19		T16	39
valid_sources[0x2c]	1100	1			T15	18		T16	31		T26	1
valid_sources[0x2d]	927	1			T9	1		T10	3		T15	33
valid_sources[0x2e]	1045	1			T6	1		T15	25		T16	36
valid_sources[0x2f]	967	1			T15	20		T16	25		T27	26
valid_sources[0x30]	1255	1			T14	2		T15	21		T16	41
valid_sources[0x31]	1270	1			T1	1		T7	2		T14	6
valid_sources[0x32]	1809	1			T2	1		T15	26		T16	33
valid_sources[0x33]	1528	1			T15	15		T16	24		T27	20
valid_sources[0x34]	995	1			T6	1		T10	105		T15	22
valid_sources[0x35]	1299	1			T15	14		T16	36		T27	22
valid_sources[0x36]	1254	1			T15	23		T16	22		T27	21
valid_sources[0x37]	1340	1			T15	33		T39	18		T16	33
valid_sources[0x38]	1241	1			T15	17		T16	20		T27	16
valid_sources[0x39]	1062	1			T15	27		T16	28		T41	1
valid_sources[0x3a]	883	1			T10	23		T15	26		T16	26
valid_sources[0x3b]	971	1			T15	23		T16	26		T27	20
valid_sources[0x3c]	1196	1			T15	32		T16	44		T27	19
valid_sources[0x3d]	1135	1			T15	29		T16	28		T27	25
valid_sources[0x3e]	1242	1			T9	1		T10	353		T15	14
valid_sources[0x3f]	1555	1			T10	7		T15	26		T16	37
valid_sources[0x40]	1333	1			T15	18		T16	37		T27	19
valid_sources[0x41]	1188	1			T15	28		T16	28		T27	14
valid_sources[0x42]	1241	1			T15	16		T16	31		T27	26
valid_sources[0x43]	1070	1			T15	14		T16	26		T27	19
valid_sources[0x44]	953	1			T6	1		T10	1		T15	7
valid_sources[0x45]	961	1			T15	30		T16	29		T27	16
valid_sources[0x46]	1325	1			T7	1		T13	3		T15	28
valid_sources[0x47]	1172	1			T1	8		T10	145		T15	39
valid_sources[0x48]	1079	1			T15	19		T16	37		T41	1
valid_sources[0x49]	1093	1			T10	9		T15	18		T16	34
valid_sources[0x4a]	1274	1			T2	1		T9	6		T15	23
valid_sources[0x4b]	988	1			T5	22		T15	21		T16	38
valid_sources[0x4c]	1034	1			T1	5		T15	23		T40	1
valid_sources[0x4d]	835	1			T15	32		T16	38		T27	23
valid_sources[0x4e]	935	1			T6	1		T15	22		T16	38
valid_sources[0x4f]	880	1			T15	42		T16	30		T41	2
valid_sources[0x50]	1402	1			T15	12		T16	26		T18	3
valid_sources[0x51]	1007	1			T15	29		T16	31		T27	22
valid_sources[0x52]	940	1			T15	14		T16	37		T27	16
valid_sources[0x53]	947	1			T15	21		T16	29		T27	20
valid_sources[0x54]	1143	1			T10	2		T15	28		T16	41
valid_sources[0x55]	1019	1			T15	16		T16	36		T27	22
valid_sources[0x56]	906	1			T15	33		T16	32		T27	15
valid_sources[0x57]	1484	1			T15	21		T16	28		T26	1
valid_sources[0x58]	879	1			T3	18		T15	13		T16	32
valid_sources[0x59]	1174	1			T10	102		T15	21		T16	27
valid_sources[0x5a]	1392	1			T15	18		T16	40		T17	2
valid_sources[0x5b]	987	1			T15	31		T16	34		T27	28
valid_sources[0x5c]	1096	1			T15	27		T16	41		T27	18
valid_sources[0x5d]	1239	1			T10	53		T15	23		T16	28
valid_sources[0x5e]	895	1			T7	2		T10	8		T15	20
valid_sources[0x5f]	829	1			T9	1		T15	16		T16	38
valid_sources[0x60]	1029	1			T10	43		T15	18		T16	33
valid_sources[0x61]	842	1			T15	21		T16	43		T27	15
valid_sources[0x62]	1049	1			T6	1		T10	121		T15	20
valid_sources[0x63]	1488	1			T15	29		T16	40		T27	26
valid_sources[0x64]	1044	1			T10	145		T15	15		T16	35
valid_sources[0x65]	1152	1			T15	22		T16	40		T27	23
valid_sources[0x66]	1069	1			T15	17		T16	35		T26	1
valid_sources[0x67]	1004	1			T15	9		T16	31		T27	18
valid_sources[0x68]	980	1			T1	1		T10	1		T15	31
valid_sources[0x69]	824	1			T15	18		T16	33		T27	24
valid_sources[0x6a]	943	1			T15	23		T16	43		T27	28
valid_sources[0x6b]	1331	1			T15	33		T16	32		T27	21
valid_sources[0x6c]	1117	1			T10	29		T15	15		T16	35
valid_sources[0x6d]	987	1			T15	21		T16	33		T27	20
valid_sources[0x6e]	937	1			T15	11		T16	21		T27	16
valid_sources[0x6f]	887	1			T6	1		T15	28		T16	38
valid_sources[0x70]	1004	1			T15	27		T16	34		T27	28
valid_sources[0x71]	1127	1			T9	4		T15	15		T16	36
valid_sources[0x72]	1247	1			T10	50		T15	25		T16	34
valid_sources[0x73]	1324	1			T6	1		T10	280		T15	17
valid_sources[0x74]	1121	1			T15	17		T16	29		T41	1
valid_sources[0x75]	1224	1			T7	4		T15	13		T16	51
valid_sources[0x76]	1426	1			T10	20		T15	20		T16	36
valid_sources[0x77]	1039	1			T6	1		T15	27		T16	25
valid_sources[0x78]	1053	1			T15	19		T16	34		T27	15
valid_sources[0x79]	1136	1			T15	22		T16	32		T17	2
valid_sources[0x7a]	1138	1			T10	22		T15	24		T16	39
valid_sources[0x7b]	1122	1			T15	14		T16	24		T17	2
valid_sources[0x7c]	998	1			T10	12		T15	22		T16	26
valid_sources[0x7d]	1368	1			T6	1		T7	1		T15	18
valid_sources[0x7e]	966	1			T15	24		T16	36		T27	21
valid_sources[0x7f]	1178	1			T15	20		T16	34		T27	15
valid_sources[0x80]	1206	1			T10	96		T15	23		T16	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64365

1

T1

1

T3

1

T6

1

values[0x0]

all_enables

biggest_size

98484

1

T1

7

T2

8

T3

8

values[0x1]

all_enables

biggest_size

97924

1

T1

7

T2

4

T3

4