Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	100.00	80.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	478675694	250650	0	0
wdog_bark_thold_rd_A	478675694	3767	0	0
wdog_bite_thold_rd_A	478675694	3489	0	0
wdog_ctrl_rd_A	478675694	3857	0	0
wdog_regwen_rd_A	478675694	3920	0	0
wkup_ctrl_rd_A	478675694	3862	0	0
wkup_thold_hi_rd_A	478675694	4048	0	0
wkup_thold_lo_rd_A	478675694	3524	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478675694	250650	0	0
T10	252933	6606	0	0
T13	14998	0	0	0
T14	33306	0	0	0
T15	270365	4885	0	0
T16	307855	8320	0	0
T19	34342	0	0	0
T24	812548	0	0	0
T25	92719	0	0	0
T27	0	4572	0	0
T33	0	6899	0	0
T34	0	12896	0	0
T35	0	4344	0	0
T36	0	3715	0	0
T37	0	2271	0	0
T38	0	8910	0	0
T39	7584	0	0	0
T40	27456	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478675694	3767	0	0
T29	0	56	0	0
T30	0	12	0	0
T57	0	19	0	0
T70	378457	544	0	0
T71	202880	208	0	0
T72	0	379	0	0
T73	0	483	0	0
T74	0	418	0	0
T75	0	529	0	0
T76	0	22	0	0
T77	51250	0	0	0
T78	54897	0	0	0
T79	64320	0	0	0
T80	442664	0	0	0
T81	36605	0	0	0
T82	9936	0	0	0
T83	57358	0	0	0
T84	153627	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478675694	3489	0	0
T28	0	8	0	0
T29	0	73	0	0
T57	0	33	0	0
T70	378457	352	0	0
T71	202880	211	0	0
T72	0	467	0	0
T73	0	368	0	0
T74	0	397	0	0
T75	0	488	0	0
T76	0	24	0	0
T77	51250	0	0	0
T78	54897	0	0	0
T79	64320	0	0	0
T80	442664	0	0	0
T81	36605	0	0	0
T82	9936	0	0	0
T83	57358	0	0	0
T84	153627	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478675694	3857	0	0
T28	0	6	0	0
T29	0	106	0	0
T30	0	3	0	0
T70	378457	491	0	0
T71	202880	236	0	0
T72	0	401	0	0
T73	0	407	0	0
T74	0	365	0	0
T75	0	451	0	0
T76	0	25	0	0
T77	51250	0	0	0
T78	54897	0	0	0
T79	64320	0	0	0
T80	442664	0	0	0
T81	36605	0	0	0
T82	9936	0	0	0
T83	57358	0	0	0
T84	153627	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478675694	3920	0	0
T28	0	1	0	0
T29	0	92	0	0
T57	0	22	0	0
T70	378457	513	0	0
T71	202880	199	0	0
T72	0	475	0	0
T73	0	423	0	0
T74	0	421	0	0
T75	0	473	0	0
T76	0	25	0	0
T77	51250	0	0	0
T78	54897	0	0	0
T79	64320	0	0	0
T80	442664	0	0	0
T81	36605	0	0	0
T82	9936	0	0	0
T83	57358	0	0	0
T84	153627	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478675694	3862	0	0
T28	0	7	0	0
T29	0	119	0	0
T30	0	4	0	0
T70	378457	442	0	0
T71	202880	238	0	0
T72	0	420	0	0
T73	0	448	0	0
T74	0	339	0	0
T75	0	469	0	0
T76	0	33	0	0
T77	51250	0	0	0
T78	54897	0	0	0
T79	64320	0	0	0
T80	442664	0	0	0
T81	36605	0	0	0
T82	9936	0	0	0
T83	57358	0	0	0
T84	153627	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478675694	4048	0	0
T28	0	5	0	0
T29	0	66	0	0
T30	0	4	0	0
T70	378457	504	0	0
T71	202880	263	0	0
T72	0	449	0	0
T73	0	477	0	0
T74	0	427	0	0
T75	0	602	0	0
T76	0	48	0	0
T77	51250	0	0	0
T78	54897	0	0	0
T79	64320	0	0	0
T80	442664	0	0	0
T81	36605	0	0	0
T82	9936	0	0	0
T83	57358	0	0	0
T84	153627	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478675694	3524	0	0
T28	0	2	0	0
T29	0	64	0	0
T30	0	5	0	0
T70	378457	435	0	0
T71	202880	225	0	0
T72	0	362	0	0
T73	0	491	0	0
T74	0	312	0	0
T75	0	359	0	0
T76	0	65	0	0
T77	51250	0	0	0
T78	54897	0	0	0
T79	64320	0	0	0
T80	442664	0	0	0
T81	36605	0	0	0
T82	9936	0	0	0
T83	57358	0	0	0
T84	153627	0	0	0