Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43991	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

331646

1

T1

16

T2

14

T3

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	94788	1			T1	1		T2	1		T3	1
values[0x0]	132663	1			T1	11		T2	9		T3	12
values[0x1]	148186	1			T1	10		T2	8		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26189	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

349448

1

T1

16

T2

14

T3

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1555	1			T12	8		T17	3		T20	1
valid_sources[0x01]	1245	1			T3	1		T12	8		T17	5
valid_sources[0x02]	1198	1			T3	1		T12	14		T15	4
valid_sources[0x03]	1344	1			T12	11		T13	2		T17	34
valid_sources[0x04]	1221	1			T12	17		T17	25		T20	1
valid_sources[0x05]	1482	1			T12	16		T17	24		T18	1
valid_sources[0x06]	1262	1			T12	6		T17	12		T214	1
valid_sources[0x07]	1420	1			T12	7		T17	27		T19	5
valid_sources[0x08]	1670	1			T2	2		T12	13		T17	2
valid_sources[0x09]	1643	1			T3	1		T12	14		T17	5
valid_sources[0x0a]	1486	1			T12	16		T14	2		T17	26
valid_sources[0x0b]	1542	1			T12	7		T17	3		T19	3
valid_sources[0x0c]	1950	1			T4	1		T12	15		T14	1
valid_sources[0x0d]	1613	1			T12	2		T17	9		T49	2
valid_sources[0x0e]	1701	1			T12	17		T17	11		T19	1
valid_sources[0x0f]	1534	1			T12	4		T17	1		T18	5
valid_sources[0x10]	1309	1			T12	11		T17	31		T19	1
valid_sources[0x11]	1571	1			T12	8		T17	20		T215	1
valid_sources[0x12]	1454	1			T12	10		T17	5		T22	25
valid_sources[0x13]	1217	1			T12	8		T13	2		T17	12
valid_sources[0x14]	1280	1			T12	7		T17	19		T49	1
valid_sources[0x15]	1211	1			T12	7		T17	107		T214	1
valid_sources[0x16]	1137	1			T12	3		T17	35		T191	1
valid_sources[0x17]	1281	1			T3	2		T12	16		T14	1
valid_sources[0x18]	1388	1			T12	13		T17	3		T18	2
valid_sources[0x19]	1213	1			T12	11		T17	1		T22	23
valid_sources[0x1a]	1429	1			T8	1		T12	6		T17	15
valid_sources[0x1b]	1117	1			T10	1		T12	3		T17	8
valid_sources[0x1c]	1603	1			T12	2		T17	26		T208	2
valid_sources[0x1d]	1137	1			T12	11		T15	2		T17	1
valid_sources[0x1e]	1419	1			T7	1		T12	4		T17	5
valid_sources[0x1f]	1292	1			T12	9		T214	1		T22	13
valid_sources[0x20]	1457	1			T12	5		T17	15		T214	1
valid_sources[0x21]	1739	1			T2	2		T12	8		T17	11
valid_sources[0x22]	1574	1			T12	1		T17	16		T19	1
valid_sources[0x23]	1292	1			T2	1		T12	9		T17	21
valid_sources[0x24]	1365	1			T12	9		T19	4		T22	31
valid_sources[0x25]	1597	1			T4	2		T12	5		T17	11
valid_sources[0x26]	1639	1			T12	15		T17	3		T22	28
valid_sources[0x27]	1755	1			T4	1		T17	37		T22	23
valid_sources[0x28]	1166	1			T2	1		T12	4		T17	42
valid_sources[0x29]	1540	1			T12	11		T17	10		T20	1
valid_sources[0x2a]	1543	1			T12	4		T14	5		T17	5
valid_sources[0x2b]	1179	1			T12	9		T209	4		T216	1
valid_sources[0x2c]	1789	1			T12	8		T17	17		T33	18
valid_sources[0x2d]	1232	1			T12	7		T14	1		T17	5
valid_sources[0x2e]	1642	1			T12	11		T17	5		T50	2
valid_sources[0x2f]	1401	1			T12	22		T17	11		T20	2
valid_sources[0x30]	1667	1			T12	6		T17	29		T19	2
valid_sources[0x31]	1236	1			T4	1		T12	5		T17	16
valid_sources[0x32]	1624	1			T12	13		T17	10		T50	1
valid_sources[0x33]	1638	1			T12	12		T17	39		T19	1
valid_sources[0x34]	1840	1			T2	1		T12	10		T15	1
valid_sources[0x35]	1278	1			T12	2		T17	8		T216	1
valid_sources[0x36]	1543	1			T12	13		T17	1		T19	1
valid_sources[0x37]	1461	1			T12	5		T17	14		T214	1
valid_sources[0x38]	1713	1			T12	10		T17	16		T29	3
valid_sources[0x39]	1286	1			T12	14		T17	21		T214	1
valid_sources[0x3a]	1572	1			T12	17		T17	3		T19	1
valid_sources[0x3b]	2082	1			T12	13		T17	16		T19	3
valid_sources[0x3c]	1332	1			T12	9		T17	29		T202	7
valid_sources[0x3d]	1728	1			T17	1		T18	1		T22	20
valid_sources[0x3e]	1169	1			T10	1		T12	8		T17	29
valid_sources[0x3f]	1560	1			T12	9		T17	15		T20	2
valid_sources[0x40]	1330	1			T4	1		T12	2		T17	24
valid_sources[0x41]	1167	1			T8	2		T12	12		T17	27
valid_sources[0x42]	1825	1			T8	2		T12	23		T17	22
valid_sources[0x43]	1769	1			T12	15		T17	5		T22	32
valid_sources[0x44]	1388	1			T12	9		T17	7		T19	1
valid_sources[0x45]	1975	1			T1	22		T12	11		T17	9
valid_sources[0x46]	1434	1			T12	4		T17	12		T20	1
valid_sources[0x47]	1571	1			T12	9		T17	4		T22	20
valid_sources[0x48]	1362	1			T12	3		T17	1		T134	1
valid_sources[0x49]	1383	1			T8	3		T12	10		T17	70
valid_sources[0x4a]	1631	1			T12	11		T15	1		T17	18
valid_sources[0x4b]	1383	1			T4	2		T12	8		T17	6
valid_sources[0x4c]	1790	1			T12	7		T13	5		T17	13
valid_sources[0x4d]	1577	1			T12	15		T17	8		T214	1
valid_sources[0x4e]	1435	1			T8	1		T12	6		T17	8
valid_sources[0x4f]	1361	1			T12	5		T17	37		T19	1
valid_sources[0x50]	1596	1			T10	1		T12	10		T17	2
valid_sources[0x51]	1508	1			T12	3		T13	1		T17	28
valid_sources[0x52]	1538	1			T12	13		T17	30		T214	1
valid_sources[0x53]	1642	1			T12	2		T17	8		T191	1
valid_sources[0x54]	1396	1			T12	5		T13	1		T17	8
valid_sources[0x55]	1764	1			T12	11		T17	4		T19	2
valid_sources[0x56]	1419	1			T12	2		T17	6		T22	22
valid_sources[0x57]	1568	1			T12	6		T15	2		T17	23
valid_sources[0x58]	1302	1			T12	5		T17	17		T19	1
valid_sources[0x59]	1710	1			T6	1		T10	2		T12	5
valid_sources[0x5a]	1193	1			T12	6		T17	2		T22	31
valid_sources[0x5b]	1451	1			T12	6		T17	23		T49	4
valid_sources[0x5c]	1272	1			T12	2		T17	32		T215	1
valid_sources[0x5d]	1265	1			T12	4		T20	1		T19	5
valid_sources[0x5e]	1481	1			T8	1		T12	12		T17	2
valid_sources[0x5f]	1344	1			T2	1		T12	11		T17	9
valid_sources[0x60]	1432	1			T12	6		T17	2		T134	1
valid_sources[0x61]	1493	1			T2	1		T12	11		T17	35
valid_sources[0x62]	1306	1			T12	6		T17	16		T19	1
valid_sources[0x63]	1142	1			T6	1		T12	14		T17	10
valid_sources[0x64]	1544	1			T8	2		T12	12		T15	1
valid_sources[0x65]	1557	1			T12	6		T17	20		T208	10
valid_sources[0x66]	1594	1			T12	9		T17	4		T19	2
valid_sources[0x67]	1816	1			T12	12		T17	14		T191	1
valid_sources[0x68]	1817	1			T12	3		T17	7		T216	1
valid_sources[0x69]	1696	1			T7	4		T12	5		T22	31
valid_sources[0x6a]	1420	1			T12	6		T17	7		T19	3
valid_sources[0x6b]	1106	1			T2	1		T12	7		T17	23
valid_sources[0x6c]	1332	1			T4	1		T6	7		T12	9
valid_sources[0x6d]	1348	1			T12	18		T17	18		T215	1
valid_sources[0x6e]	1512	1			T4	1		T12	6		T17	1
valid_sources[0x6f]	2026	1			T12	6		T17	31		T18	2
valid_sources[0x70]	1974	1			T12	3		T17	1		T20	1
valid_sources[0x71]	1512	1			T17	16		T49	1		T19	1
valid_sources[0x72]	1448	1			T6	12		T12	6		T17	19
valid_sources[0x73]	1277	1			T12	11		T17	4		T22	27
valid_sources[0x74]	1500	1			T12	16		T17	2		T19	3
valid_sources[0x75]	1231	1			T12	11		T17	2		T134	2
valid_sources[0x76]	1238	1			T12	4		T17	53		T19	2
valid_sources[0x77]	1912	1			T12	17		T17	19		T215	1
valid_sources[0x78]	1389	1			T12	9		T17	36		T31	22
valid_sources[0x79]	1340	1			T12	2		T17	23		T29	1
valid_sources[0x7a]	1184	1			T12	19		T17	16		T29	1
valid_sources[0x7b]	1316	1			T8	2		T12	14		T17	11
valid_sources[0x7c]	1411	1			T12	9		T17	3		T19	1
valid_sources[0x7d]	1622	1			T17	27		T20	1		T215	1
valid_sources[0x7e]	1206	1			T8	1		T10	1		T12	6
valid_sources[0x7f]	1251	1			T12	6		T17	4		T30	4
valid_sources[0x80]	1186	1			T12	3		T17	49		T29	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

81928

1

T2

1

T3

1

T8

1

values[0x0]

all_enables

biggest_size

125119

1

T1

8

T2

7

T3

8

values[0x1]

all_enables

biggest_size

124599

1

T1

8

T2

6

T3

6