Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.00	100.00	80.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	660394607	332995	0	0
wdog_bark_thold_rd_A	660394607	8235	0	0
wdog_bite_thold_rd_A	660394607	6844	0	0
wdog_ctrl_rd_A	660394607	7238	0	0
wdog_regwen_rd_A	660394607	7947	0	0
wkup_ctrl_rd_A	660394607	6994	0	0
wkup_thold_hi_rd_A	660394607	7518	0	0
wkup_thold_lo_rd_A	660394607	7267	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660394607	332995	0	0
T12	177694	1552	0	0
T13	9686	0	0	0
T14	13087	0	0	0
T15	7578	0	0	0
T16	551036	0	0	0
T17	150350	3063	0	0
T18	839379	0	0	0
T21	405183	0	0	0
T22	0	5484	0	0
T23	208191	0	0	0
T28	27776	0	0	0
T34	0	6496	0	0
T43	0	5984	0	0
T44	0	12039	0	0
T45	0	8249	0	0
T46	0	4751	0	0
T47	0	9649	0	0
T48	0	10135	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660394607	8235	0	0
T12	177694	210	0	0
T13	9686	0	0	0
T14	13087	0	0	0
T15	7578	0	0	0
T16	551036	0	0	0
T17	150350	0	0	0
T18	839379	0	0	0
T21	405183	0	0	0
T22	0	798	0	0
T23	208191	0	0	0
T28	27776	0	0	0
T34	0	225	0	0
T43	0	286	0	0
T46	0	424	0	0
T75	0	324	0	0
T76	0	754	0	0
T77	0	230	0	0
T78	0	138	0	0
T79	0	900	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660394607	6844	0	0
T12	177694	195	0	0
T13	9686	0	0	0
T14	13087	0	0	0
T15	7578	0	0	0
T16	551036	0	0	0
T17	150350	0	0	0
T18	839379	0	0	0
T21	405183	0	0	0
T22	0	703	0	0
T23	208191	0	0	0
T28	27776	0	0	0
T34	0	248	0	0
T43	0	273	0	0
T46	0	499	0	0
T75	0	175	0	0
T76	0	737	0	0
T77	0	292	0	0
T78	0	125	0	0
T79	0	650	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660394607	7238	0	0
T12	177694	193	0	0
T13	9686	0	0	0
T14	13087	0	0	0
T15	7578	0	0	0
T16	551036	0	0	0
T17	150350	0	0	0
T18	839379	0	0	0
T21	405183	0	0	0
T22	0	794	0	0
T23	208191	0	0	0
T28	27776	0	0	0
T34	0	236	0	0
T43	0	217	0	0
T46	0	381	0	0
T75	0	148	0	0
T76	0	679	0	0
T77	0	292	0	0
T78	0	82	0	0
T79	0	874	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660394607	7947	0	0
T12	177694	160	0	0
T13	9686	0	0	0
T14	13087	0	0	0
T15	7578	0	0	0
T16	551036	0	0	0
T17	150350	0	0	0
T18	839379	0	0	0
T21	405183	0	0	0
T22	0	727	0	0
T23	208191	0	0	0
T28	27776	0	0	0
T34	0	385	0	0
T43	0	276	0	0
T46	0	459	0	0
T75	0	224	0	0
T76	0	843	0	0
T77	0	300	0	0
T78	0	86	0	0
T79	0	752	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660394607	6994	0	0
T12	177694	190	0	0
T13	9686	0	0	0
T14	13087	0	0	0
T15	7578	0	0	0
T16	551036	0	0	0
T17	150350	0	0	0
T18	839379	0	0	0
T21	405183	0	0	0
T22	0	731	0	0
T23	208191	0	0	0
T28	27776	0	0	0
T34	0	336	0	0
T43	0	273	0	0
T46	0	415	0	0
T75	0	190	0	0
T76	0	723	0	0
T77	0	270	0	0
T78	0	78	0	0
T79	0	612	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660394607	7518	0	0
T12	177694	245	0	0
T13	9686	0	0	0
T14	13087	0	0	0
T15	7578	0	0	0
T16	551036	0	0	0
T17	150350	0	0	0
T18	839379	0	0	0
T21	405183	0	0	0
T22	0	633	0	0
T23	208191	0	0	0
T28	27776	0	0	0
T34	0	305	0	0
T43	0	359	0	0
T46	0	437	0	0
T75	0	277	0	0
T76	0	780	0	0
T77	0	311	0	0
T78	0	106	0	0
T79	0	680	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660394607	7267	0	0
T12	177694	162	0	0
T13	9686	0	0	0
T14	13087	0	0	0
T15	7578	0	0	0
T16	551036	0	0	0
T17	150350	0	0	0
T18	839379	0	0	0
T21	405183	0	0	0
T22	0	709	0	0
T23	208191	0	0	0
T28	27776	0	0	0
T34	0	186	0	0
T43	0	231	0	0
T46	0	401	0	0
T75	0	220	0	0
T76	0	746	0	0
T77	0	267	0	0
T78	0	148	0	0
T79	0	744	0	0