Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40353	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

304612

1

T1

12

T2

14

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	88349	1			T1	1		T2	1		T3	1
values[0x0]	121543	1			T1	6		T2	9		T3	9
values[0x1]	135073	1			T1	12		T2	12		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24504	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

320461

1

T1

12

T2

15

T3

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1482	1			T6	4		T13	20		T32	35
valid_sources[0x01]	1276	1			T6	21		T13	39		T17	1
valid_sources[0x02]	1872	1			T6	19		T13	37		T22	2
valid_sources[0x03]	1312	1			T6	10		T13	36		T23	8
valid_sources[0x04]	1306	1			T6	24		T13	24		T18	5
valid_sources[0x05]	1336	1			T6	7		T13	20		T23	3
valid_sources[0x06]	1502	1			T6	21		T13	23		T126	1
valid_sources[0x07]	1123	1			T1	2		T6	17		T13	10
valid_sources[0x08]	1360	1			T6	24		T13	29		T14	22
valid_sources[0x09]	1165	1			T6	20		T13	30		T22	1
valid_sources[0x0a]	1115	1			T6	7		T13	38		T30	13
valid_sources[0x0b]	1164	1			T6	18		T13	38		T39	1
valid_sources[0x0c]	1310	1			T6	16		T13	29		T16	1
valid_sources[0x0d]	1458	1			T5	1		T6	9		T13	36
valid_sources[0x0e]	1268	1			T6	29		T7	3		T13	25
valid_sources[0x0f]	1220	1			T6	14		T13	27		T16	2
valid_sources[0x10]	1261	1			T6	12		T13	30		T16	3
valid_sources[0x11]	1322	1			T6	19		T13	33		T17	3
valid_sources[0x12]	1537	1			T6	3		T10	3		T13	31
valid_sources[0x13]	1152	1			T6	14		T13	24		T32	22
valid_sources[0x14]	2068	1			T6	18		T13	39		T14	212
valid_sources[0x15]	1141	1			T3	3		T6	1		T13	23
valid_sources[0x16]	1296	1			T6	23		T10	10		T13	26
valid_sources[0x17]	1218	1			T1	1		T6	4		T13	23
valid_sources[0x18]	1695	1			T6	17		T13	25		T16	10
valid_sources[0x19]	1112	1			T6	42		T7	1		T13	36
valid_sources[0x1a]	1204	1			T6	20		T13	30		T18	1
valid_sources[0x1b]	1314	1			T6	50		T13	27		T17	3
valid_sources[0x1c]	1112	1			T6	63		T10	4		T13	22
valid_sources[0x1d]	1173	1			T6	19		T13	30		T16	3
valid_sources[0x1e]	1267	1			T6	10		T13	39		T39	1
valid_sources[0x1f]	1246	1			T6	8		T13	31		T18	1
valid_sources[0x20]	1327	1			T6	12		T13	29		T22	1
valid_sources[0x21]	1328	1			T6	19		T13	21		T32	29
valid_sources[0x22]	1189	1			T6	27		T13	23		T18	3
valid_sources[0x23]	1324	1			T6	12		T13	31		T17	2
valid_sources[0x24]	1261	1			T6	6		T13	30		T18	3
valid_sources[0x25]	1744	1			T6	2		T9	1		T13	31
valid_sources[0x26]	1363	1			T6	29		T13	30		T18	2
valid_sources[0x27]	1391	1			T6	31		T13	29		T18	1
valid_sources[0x28]	1462	1			T6	8		T13	38		T17	1
valid_sources[0x29]	1316	1			T6	1		T13	28		T30	125
valid_sources[0x2a]	1207	1			T1	1		T6	13		T13	31
valid_sources[0x2b]	1475	1			T1	3		T6	12		T13	41
valid_sources[0x2c]	1260	1			T6	5		T13	35		T18	1
valid_sources[0x2d]	1409	1			T6	22		T13	43		T17	1
valid_sources[0x2e]	1453	1			T6	14		T13	27		T14	3
valid_sources[0x2f]	1086	1			T6	37		T13	28		T17	4
valid_sources[0x30]	1572	1			T6	18		T13	38		T126	2
valid_sources[0x31]	1179	1			T6	28		T13	30		T18	2
valid_sources[0x32]	1720	1			T6	20		T13	26		T16	3
valid_sources[0x33]	1337	1			T3	2		T6	8		T13	29
valid_sources[0x34]	1424	1			T6	19		T13	16		T17	1
valid_sources[0x35]	1473	1			T6	26		T13	32		T14	4
valid_sources[0x36]	1228	1			T6	18		T13	22		T17	4
valid_sources[0x37]	1653	1			T6	11		T13	37		T17	4
valid_sources[0x38]	1104	1			T3	2		T6	16		T13	29
valid_sources[0x39]	1205	1			T6	14		T7	1		T8	20
valid_sources[0x3a]	1309	1			T6	15		T13	40		T22	1
valid_sources[0x3b]	1641	1			T6	28		T13	32		T17	1
valid_sources[0x3c]	1242	1			T1	1		T6	8		T13	41
valid_sources[0x3d]	1477	1			T6	19		T13	31		T75	3
valid_sources[0x3e]	1011	1			T6	30		T13	17		T32	35
valid_sources[0x3f]	1112	1			T6	7		T13	25		T14	1
valid_sources[0x40]	1386	1			T6	23		T13	31		T17	1
valid_sources[0x41]	1249	1			T6	37		T13	40		T32	27
valid_sources[0x42]	1252	1			T6	12		T13	27		T17	1
valid_sources[0x43]	1285	1			T6	23		T13	35		T18	1
valid_sources[0x44]	1383	1			T6	40		T13	33		T16	2
valid_sources[0x45]	1217	1			T6	7		T13	26		T30	1
valid_sources[0x46]	1194	1			T6	7		T13	40		T18	1
valid_sources[0x47]	1104	1			T6	10		T13	26		T18	2
valid_sources[0x48]	1513	1			T6	9		T13	30		T22	5
valid_sources[0x49]	1334	1			T3	3		T6	22		T13	41
valid_sources[0x4a]	1243	1			T6	2		T13	19		T32	30
valid_sources[0x4b]	1494	1			T6	17		T13	28		T17	5
valid_sources[0x4c]	1284	1			T6	10		T13	29		T39	1
valid_sources[0x4d]	1581	1			T6	7		T13	31		T18	1
valid_sources[0x4e]	1427	1			T6	14		T7	3		T13	43
valid_sources[0x4f]	1195	1			T6	20		T13	37		T39	1
valid_sources[0x50]	1343	1			T6	9		T13	47		T14	54
valid_sources[0x51]	1449	1			T6	8		T13	23		T32	34
valid_sources[0x52]	1173	1			T6	20		T9	1		T13	25
valid_sources[0x53]	1353	1			T6	14		T13	26		T32	19
valid_sources[0x54]	1458	1			T6	20		T9	2		T13	23
valid_sources[0x55]	1499	1			T6	30		T13	29		T14	1
valid_sources[0x56]	1501	1			T6	29		T9	1		T13	34
valid_sources[0x57]	1749	1			T6	25		T13	25		T23	5
valid_sources[0x58]	1367	1			T6	17		T13	43		T14	111
valid_sources[0x59]	1425	1			T6	22		T13	33		T16	5
valid_sources[0x5a]	1114	1			T6	10		T13	31		T14	14
valid_sources[0x5b]	1355	1			T6	36		T13	30		T18	3
valid_sources[0x5c]	1110	1			T6	16		T13	34		T16	4
valid_sources[0x5d]	1311	1			T6	12		T13	19		T39	1
valid_sources[0x5e]	1693	1			T6	3		T13	23		T17	1
valid_sources[0x5f]	1247	1			T6	14		T13	31		T16	8
valid_sources[0x60]	1945	1			T6	81		T13	33		T32	38
valid_sources[0x61]	1238	1			T6	12		T13	26		T17	6
valid_sources[0x62]	1201	1			T6	15		T13	20		T126	1
valid_sources[0x63]	1307	1			T6	19		T13	18		T17	2
valid_sources[0x64]	1308	1			T6	2		T13	33		T32	27
valid_sources[0x65]	1313	1			T6	29		T13	31		T18	2
valid_sources[0x66]	1182	1			T6	23		T13	33		T32	18
valid_sources[0x67]	1066	1			T3	1		T5	4		T6	9
valid_sources[0x68]	1575	1			T6	21		T13	20		T30	11
valid_sources[0x69]	1207	1			T6	32		T13	40		T16	2
valid_sources[0x6a]	1282	1			T6	16		T13	26		T39	1
valid_sources[0x6b]	1155	1			T6	39		T13	31		T32	32
valid_sources[0x6c]	1268	1			T6	17		T13	14		T16	2
valid_sources[0x6d]	1096	1			T6	11		T13	18		T16	4
valid_sources[0x6e]	1083	1			T6	8		T13	30		T16	1
valid_sources[0x6f]	1132	1			T6	6		T13	23		T18	2
valid_sources[0x70]	1201	1			T6	37		T13	31		T22	1
valid_sources[0x71]	1145	1			T6	38		T13	33		T16	1
valid_sources[0x72]	1178	1			T6	29		T13	31		T32	33
valid_sources[0x73]	1146	1			T13	23		T17	5		T32	18
valid_sources[0x74]	1459	1			T6	17		T13	32		T14	1
valid_sources[0x75]	1339	1			T6	13		T9	1		T13	30
valid_sources[0x76]	1133	1			T6	11		T13	41		T17	3
valid_sources[0x77]	1362	1			T6	6		T13	29		T38	8
valid_sources[0x78]	1153	1			T6	39		T13	19		T14	1
valid_sources[0x79]	1489	1			T6	26		T13	31		T16	1
valid_sources[0x7a]	1782	1			T6	1		T7	1		T9	1
valid_sources[0x7b]	1198	1			T6	11		T13	41		T14	4
valid_sources[0x7c]	1915	1			T1	2		T6	16		T13	26
valid_sources[0x7d]	1542	1			T6	10		T9	1		T13	41
valid_sources[0x7e]	1554	1			T6	15		T13	21		T16	2
valid_sources[0x7f]	1250	1			T6	12		T7	1		T13	33
valid_sources[0x80]	1300	1			T6	3		T13	22		T30	187

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

76033

1

T1

1

T5

1

T6

1030

values[0x0]

all_enables

biggest_size

114648

1

T1

4

T2

5

T3

5

values[0x1]

all_enables

biggest_size

113931

1

T1

7

T2

9

T3

6