Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40244	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

300154

1

T1

17

T2

12

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	85372	1			T1	1		T2	1		T3	1
values[0x0]	121272	1			T1	13		T2	9		T3	11
values[0x1]	133754	1			T1	8		T2	8		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24770	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

315628

1

T1

18

T2

12

T3

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	903	1			T21	1		T26	18		T28	26
valid_sources[0x01]	1732	1			T7	2		T21	183		T26	12
valid_sources[0x02]	1064	1			T26	22		T28	2		T52	1
valid_sources[0x03]	1114	1			T26	11		T28	6		T35	1
valid_sources[0x04]	1162	1			T21	19		T23	3		T26	15
valid_sources[0x05]	2128	1			T23	1		T26	15		T28	20
valid_sources[0x06]	1685	1			T20	1		T21	76		T26	12
valid_sources[0x07]	877	1			T2	1		T26	9		T28	51
valid_sources[0x08]	1346	1			T23	2		T26	13		T28	10
valid_sources[0x09]	1190	1			T5	2		T22	2		T26	2
valid_sources[0x0a]	1004	1			T5	1		T21	2		T26	6
valid_sources[0x0b]	1585	1			T26	11		T28	3		T30	19
valid_sources[0x0c]	1244	1			T26	30		T38	4		T28	2
valid_sources[0x0d]	992	1			T20	3		T21	6		T26	30
valid_sources[0x0e]	1153	1			T21	3		T26	11		T30	20
valid_sources[0x0f]	1627	1			T22	1		T26	5		T52	1
valid_sources[0x10]	1316	1			T21	196		T22	1		T26	19
valid_sources[0x11]	988	1			T19	20		T26	4		T28	3
valid_sources[0x12]	1355	1			T21	180		T26	17		T28	2
valid_sources[0x13]	1195	1			T21	20		T26	9		T30	21
valid_sources[0x14]	1083	1			T21	1		T26	35		T28	23
valid_sources[0x15]	1193	1			T26	22		T28	31		T35	2
valid_sources[0x16]	1227	1			T26	8		T28	11		T30	20
valid_sources[0x17]	1028	1			T26	17		T28	35		T30	24
valid_sources[0x18]	1250	1			T26	22		T28	32		T35	1
valid_sources[0x19]	1832	1			T21	1		T26	9		T28	8
valid_sources[0x1a]	1140	1			T26	15		T51	1		T28	4
valid_sources[0x1b]	1176	1			T4	1		T5	3		T26	15
valid_sources[0x1c]	1265	1			T21	6		T26	19		T28	21
valid_sources[0x1d]	1196	1			T21	1		T26	8		T28	28
valid_sources[0x1e]	1425	1			T21	79		T26	6		T28	13
valid_sources[0x1f]	1361	1			T18	1		T26	12		T28	8
valid_sources[0x20]	1229	1			T5	1		T7	2		T26	21
valid_sources[0x21]	1182	1			T21	1		T26	14		T38	1
valid_sources[0x22]	2063	1			T21	7		T26	20		T28	2
valid_sources[0x23]	974	1			T14	3		T26	19		T37	7
valid_sources[0x24]	1223	1			T20	1		T26	26		T28	5
valid_sources[0x25]	1033	1			T26	9		T28	8		T35	5
valid_sources[0x26]	1303	1			T26	8		T28	3		T35	85
valid_sources[0x27]	1856	1			T16	22		T26	7		T28	1
valid_sources[0x28]	1183	1			T14	2		T18	1		T25	3
valid_sources[0x29]	989	1			T2	1		T14	1		T17	20
valid_sources[0x2a]	922	1			T26	8		T28	6		T30	29
valid_sources[0x2b]	1085	1			T20	2		T21	1		T26	17
valid_sources[0x2c]	1210	1			T21	1		T26	32		T28	1
valid_sources[0x2d]	1058	1			T21	3		T23	1		T26	6
valid_sources[0x2e]	1303	1			T14	3		T21	1		T26	9
valid_sources[0x2f]	1668	1			T14	2		T15	19		T26	8
valid_sources[0x30]	979	1			T18	1		T21	2		T26	7
valid_sources[0x31]	1220	1			T26	1		T28	64		T35	2
valid_sources[0x32]	905	1			T26	19		T28	1		T30	29
valid_sources[0x33]	1474	1			T26	15		T35	3		T30	18
valid_sources[0x34]	1558	1			T26	17		T28	18		T30	21
valid_sources[0x35]	1580	1			T21	243		T26	25		T35	1
valid_sources[0x36]	1542	1			T5	2		T21	9		T26	4
valid_sources[0x37]	2295	1			T21	2		T26	11		T28	12
valid_sources[0x38]	942	1			T26	41		T28	7		T30	22
valid_sources[0x39]	1181	1			T7	1		T21	1		T26	6
valid_sources[0x3a]	783	1			T4	1		T26	19		T28	2
valid_sources[0x3b]	1025	1			T29	3		T26	16		T28	36
valid_sources[0x3c]	1365	1			T21	5		T26	10		T28	5
valid_sources[0x3d]	1756	1			T26	7		T28	22		T35	29
valid_sources[0x3e]	1269	1			T18	1		T21	1		T26	9
valid_sources[0x3f]	1236	1			T21	2		T26	19		T28	13
valid_sources[0x40]	1729	1			T26	25		T28	41		T35	4
valid_sources[0x41]	1364	1			T21	105		T26	7		T28	17
valid_sources[0x42]	1253	1			T26	7		T28	15		T35	206
valid_sources[0x43]	1262	1			T21	2		T26	13		T28	12
valid_sources[0x44]	1643	1			T7	1		T21	186		T26	20
valid_sources[0x45]	1515	1			T29	3		T26	15		T28	33
valid_sources[0x46]	1502	1			T21	74		T26	14		T28	25
valid_sources[0x47]	1413	1			T26	31		T28	10		T35	7
valid_sources[0x48]	1206	1			T21	68		T29	1		T26	29
valid_sources[0x49]	1560	1			T10	7		T18	1		T26	5
valid_sources[0x4a]	1897	1			T21	239		T22	1		T26	15
valid_sources[0x4b]	1597	1			T21	14		T26	10		T28	2
valid_sources[0x4c]	1332	1			T5	2		T20	2		T26	9
valid_sources[0x4d]	1530	1			T4	2		T7	1		T18	1
valid_sources[0x4e]	1227	1			T26	23		T28	11		T35	22
valid_sources[0x4f]	1161	1			T21	1		T26	14		T28	6
valid_sources[0x50]	869	1			T18	1		T26	11		T28	10
valid_sources[0x51]	892	1			T26	19		T37	2		T28	13
valid_sources[0x52]	1258	1			T2	1		T21	6		T23	2
valid_sources[0x53]	1839	1			T21	136		T25	11		T26	11
valid_sources[0x54]	1633	1			T26	40		T28	3		T35	127
valid_sources[0x55]	1460	1			T7	1		T26	15		T28	1
valid_sources[0x56]	1977	1			T13	22		T26	1		T28	24
valid_sources[0x57]	1333	1			T18	3		T21	2		T26	5
valid_sources[0x58]	1355	1			T5	1		T26	18		T28	9
valid_sources[0x59]	1585	1			T26	9		T28	8		T35	134
valid_sources[0x5a]	879	1			T18	1		T21	1		T26	17
valid_sources[0x5b]	1383	1			T26	23		T28	1		T52	1
valid_sources[0x5c]	1217	1			T21	1		T26	11		T28	3
valid_sources[0x5d]	1521	1			T7	2		T22	2		T26	4
valid_sources[0x5e]	1185	1			T21	51		T26	7		T28	11
valid_sources[0x5f]	1388	1			T26	6		T28	19		T35	5
valid_sources[0x60]	1327	1			T26	7		T28	20		T30	18
valid_sources[0x61]	1035	1			T21	2		T26	10		T35	73
valid_sources[0x62]	936	1			T18	2		T26	14		T35	4
valid_sources[0x63]	1466	1			T21	1		T26	11		T27	2
valid_sources[0x64]	1295	1			T26	5		T28	18		T35	48
valid_sources[0x65]	1116	1			T14	1		T23	1		T26	10
valid_sources[0x66]	1151	1			T5	1		T26	26		T28	36
valid_sources[0x67]	1372	1			T21	21		T26	9		T28	4
valid_sources[0x68]	1397	1			T21	2		T26	13		T28	6
valid_sources[0x69]	1058	1			T2	1		T21	1		T26	2
valid_sources[0x6a]	1478	1			T7	1		T26	11		T28	10
valid_sources[0x6b]	1856	1			T26	14		T28	3		T35	165
valid_sources[0x6c]	939	1			T26	22		T28	5		T30	25
valid_sources[0x6d]	965	1			T26	29		T37	5		T28	11
valid_sources[0x6e]	953	1			T18	1		T21	5		T26	26
valid_sources[0x6f]	1414	1			T2	3		T26	19		T28	8
valid_sources[0x70]	1121	1			T20	1		T26	3		T28	18
valid_sources[0x71]	1041	1			T21	12		T26	5		T28	26
valid_sources[0x72]	933	1			T26	15		T28	19		T35	1
valid_sources[0x73]	1600	1			T26	2		T28	18		T35	17
valid_sources[0x74]	1155	1			T21	1		T26	12		T28	4
valid_sources[0x75]	1687	1			T26	13		T28	25		T35	1
valid_sources[0x76]	1113	1			T21	1		T26	21		T37	1
valid_sources[0x77]	1392	1			T26	20		T28	30		T30	26
valid_sources[0x78]	1769	1			T21	1		T26	6		T28	34
valid_sources[0x79]	1333	1			T28	8		T35	43		T30	20
valid_sources[0x7a]	1184	1			T21	30		T26	13		T28	11
valid_sources[0x7b]	1363	1			T21	39		T22	1		T23	2
valid_sources[0x7c]	1169	1			T21	3		T26	20		T28	6
valid_sources[0x7d]	899	1			T26	3		T28	15		T30	14
valid_sources[0x7e]	1311	1			T14	2		T21	1		T26	9
valid_sources[0x7f]	1554	1			T7	1		T26	6		T28	2
valid_sources[0x80]	1439	1			T20	1		T26	3		T28	44

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

73344

1

T1

1

T4

1

T5

1

values[0x0]

all_enables

biggest_size

113894

1

T1

11

T2

7

T3

10

values[0x1]

all_enables

biggest_size

112916

1

T1

5

T2

5

T3

6